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52 lines
1.9 KiB
Diff
52 lines
1.9 KiB
Diff
From e1b03c0d3dfb337c7f462ea7e146e727dbe35040 Mon Sep 17 00:00:00 2001
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From: Dave Airlie <airlied@redhat.com>
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Date: Mon, 18 Dec 2023 16:47:56 +1000
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Subject: [PATCH] intel/compiler: move gen5 final pass to actually be final
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pass
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This got broken by the register conversion, this pass needs to be
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after all the others.
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Fixes: ce75c3c3fea9 ("intel: Switch to intrinsic-based registers")
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---
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src/intel/compiler/brw_nir.c | 17 +++++++++--------
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1 file changed, 9 insertions(+), 8 deletions(-)
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diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c
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index 8da98b0fbfd..c36269fd015 100644
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--- a/src/intel/compiler/brw_nir.c
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+++ b/src/intel/compiler/brw_nir.c
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@@ -1753,14 +1753,6 @@ brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler,
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if (OPT(nir_opt_rematerialize_compares))
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OPT(nir_opt_dce);
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- /* This is the last pass we run before we start emitting stuff. It
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- * determines when we need to insert boolean resolves on Gen <= 5. We
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- * run it last because it stashes data in instr->pass_flags and we don't
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- * want that to be squashed by other NIR passes.
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- */
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- if (devinfo->ver <= 5)
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- brw_nir_analyze_boolean_resolves(nir);
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-
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OPT(nir_opt_dce);
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/* The mesh stages require this pass to be called at the last minute,
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@@ -1773,6 +1765,15 @@ brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler,
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brw_nir_adjust_payload(nir, compiler);
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nir_trivialize_registers(nir);
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+
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+ /* This is the last pass we run before we start emitting stuff. It
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+ * determines when we need to insert boolean resolves on Gen <= 5. We
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+ * run it last because it stashes data in instr->pass_flags and we don't
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+ * want that to be squashed by other NIR passes.
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+ */
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+ if (devinfo->ver <= 5)
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+ brw_nir_analyze_boolean_resolves(nir);
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+
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nir_sweep(nir);
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if (unlikely(debug_enabled)) {
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--
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2.43.0
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