From f3da2d81a7542bb72de27e70184273e176112538 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Mon, 9 Mar 2009 05:41:34 +0000 Subject: [PATCH] - radeon-rewrite.patch: update with swtcl and r100 bugfixes --- mesa.spec | 2 +- radeon-rewrite.patch | 3335 ++++++++++++++++++++++++++++-------------- 2 files changed, 2235 insertions(+), 1102 deletions(-) diff --git a/mesa.spec b/mesa.spec index 165761f..4737d6b 100644 --- a/mesa.spec +++ b/mesa.spec @@ -20,7 +20,7 @@ Summary: Mesa graphics libraries Name: mesa Version: 7.3 -Release: 10%{?dist} +Release: 11%{?dist} License: MIT Group: System Environment/Libraries URL: http://www.mesa3d.org diff --git a/radeon-rewrite.patch b/radeon-rewrite.patch index 7b921c5..27f21d2 100644 --- a/radeon-rewrite.patch +++ b/radeon-rewrite.patch @@ -1,3 +1,15 @@ +commit 6c28708e141d047fc44369eac08cfb9a47f22c87 +Author: Dave Airlie +Date: Mon Mar 9 13:51:39 2009 +1000 + + radeon/r200/r300: update from latest radeon-rewrite branch + +commit 38262b6fc16f627a66e1475b729047ffe8258803 +Author: Dave Airlie +Date: Mon Mar 9 13:46:44 2009 +1000 + + r300: remove some links + commit 263b887d85e3eac9a32673c8ed3004c3129ce997 Author: Dave Airlie Date: Sun Feb 15 17:03:47 2009 +1000 @@ -812,7 +824,7 @@ index e163377..ae31bcb 100644 - cmd[0].wait.flags = flags; -} diff --git a/src/mesa/drivers/dri/r200/r200_context.c b/src/mesa/drivers/dri/r200/r200_context.c -index 5531e0a..a744469 100644 +index 5531e0a..10a6362 100644 --- a/src/mesa/drivers/dri/r200/r200_context.c +++ b/src/mesa/drivers/dri/r200/r200_context.c @@ -54,7 +54,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. @@ -924,9 +936,9 @@ index 5531e0a..a744469 100644 +{ + radeon->vtbl.get_lock = r200_get_lock; + radeon->vtbl.update_viewport_offset = r200UpdateViewportOffset; -+ radeon->vtbl.update_draw_buffer = r200UpdateDrawBuffer; + radeon->vtbl.emit_cs_header = r200_vtbl_emit_cs_header; + radeon->vtbl.swtcl_flush = r200_swtcl_flush; ++ radeon->vtbl.fallback = r200Fallback; +} + @@ -1989,7 +2001,7 @@ index d514b28..85c1b7b 100644 } } diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.c b/src/mesa/drivers/dri/r200/r200_ioctl.c -index 0741e57..c08968f 100644 +index 0741e57..1ab5a82 100644 --- a/src/mesa/drivers/dri/r200/r200_ioctl.c +++ b/src/mesa/drivers/dri/r200/r200_ioctl.c @@ -41,6 +41,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. @@ -2001,7 +2013,7 @@ index 0741e57..c08968f 100644 #include "r200_context.h" #include "r200_state.h" #include "r200_ioctl.h" -@@ -54,635 +56,28 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +@@ -54,635 +56,45 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define R200_TIMEOUT 512 #define R200_IDLE_RETRY 16 @@ -2478,10 +2490,9 @@ index 0741e57..c08968f 100644 - assert(dPriv); - assert(dPriv->driContextPriv); - assert(dPriv->driContextPriv->driverPrivate); -+ if (flags & (RADEON_FRONT | RADEON_BACK)) { - +- - rmesa = (r200ContextPtr) dPriv->driContextPriv->driverPrivate; - +- - if ( R200_DEBUG & DEBUG_IOCTL ) { - fprintf(stderr, "%s: pfCurrentPage: %d\n", __FUNCTION__, - rmesa->sarea->pfCurrentPage); @@ -2494,10 +2505,8 @@ index 0741e57..c08968f 100644 - UNLOCK_HARDWARE( rmesa ); - usleep( 10000 ); /* throttle invisible client 10ms */ - return; - } -+ -+ if ((flags & (RADEON_DEPTH | RADEON_STENCIL)) -+ && (flags & RADEON_CLEAR_FASTZ)) { +- } ++ GLuint mask = 0; - /* Need to do this for the perf box placement: - */ @@ -2507,7 +2516,9 @@ index 0741e57..c08968f 100644 - b[0] = box[0]; - rmesa->sarea->nbox = 1; - } -- ++ if (flags & RADEON_FRONT) ++ mask |= BUFFER_BIT_FRONT_LEFT; + - /* Throttle the frame rate -- only allow a few pending swap buffers - * request at a time. - */ @@ -2517,21 +2528,31 @@ index 0741e57..c08968f 100644 - if ( missed_target ) { - rmesa->swap_missed_count++; - (void) (*psp->systemTime->getUST)( & rmesa->swap_missed_ust ); - } +- } - LOCK_HARDWARE( rmesa ); ++ if (flags & RADEON_BACK) ++ mask |= BUFFER_BIT_BACK_LEFT; - ret = drmCommandNone( rmesa->dri.fd, DRM_RADEON_FLIP ); -- ++ if (flags & RADEON_DEPTH) ++ mask |= BUFFER_BIT_DEPTH; + - UNLOCK_HARDWARE( rmesa ); -- ++ if (flags & RADEON_STENCIL) ++ mask |= BUFFER_BIT_STENCIL; + - if ( ret ) { - fprintf( stderr, "DRM_RADEON_FLIP: return = %d\n", ret ); - exit( 1 ); - } -- ++#if 1 ++ _swrast_Clear(ctx, mask); ++#else ++ if (flags & (RADEON_FRONT | RADEON_BACK)) { + - rmesa->swap_count++; - (void) (*psp->systemTime->getUST)( & rmesa->swap_ust ); -- + -#if 000 - if ( rmesa->sarea->pfCurrentPage == 1 ) { - rmesa->state.color.drawOffset = rmesa->r200Screen->frontOffset; @@ -2539,15 +2560,18 @@ index 0741e57..c08968f 100644 - } else { - rmesa->state.color.drawOffset = rmesa->r200Screen->backOffset; - rmesa->state.color.drawPitch = rmesa->r200Screen->backPitch; -- } -- + } ++ ++ if ((flags & (RADEON_DEPTH | RADEON_STENCIL)) ++ && (flags & RADEON_CLEAR_FASTZ)) { + - R200_STATECHANGE( rmesa, ctx ); - rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = rmesa->state.color.drawOffset - + rmesa->r200Screen->fbLocation; - rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = rmesa->state.color.drawPitch; - if (rmesa->sarea->tiling_enabled) { - rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= R200_COLOR_TILE_ENABLE; -- } + } -#else - /* Get ready for drawing next frame. Update the renderbuffers' - * flippedOffset/Pitch fields so we draw into the right place. @@ -2557,7 +2581,7 @@ index 0741e57..c08968f 100644 - - - r200UpdateDrawBuffer(rmesa->glCtx); --#endif + #endif } - @@ -2573,10 +2597,7 @@ index 0741e57..c08968f 100644 - GLuint color_mask = 0; - GLint ret, i; - GLint cx, cy, cw, ch; -+ __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable; -+ GLint cx, cy, cw, ch, ret; -+ GLuint i; - +- - if ( R200_DEBUG & DEBUG_IOCTL ) { - fprintf( stderr, "r200Clear\n"); - } @@ -2606,7 +2627,10 @@ index 0741e57..c08968f 100644 - flags |= RADEON_DEPTH; - mask &= ~BUFFER_BIT_DEPTH; - } -- ++ __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable; ++ GLint cx, cy, cw, ch, ret; ++ GLuint i; + - if ( (mask & BUFFER_BIT_STENCIL) && rmesa->state.stencil.hwBuffer ) { - flags |= RADEON_STENCIL; - mask &= ~BUFFER_BIT_STENCIL; @@ -2647,7 +2671,7 @@ index 0741e57..c08968f 100644 /* Throttle the number of clear ioctls we do. */ -@@ -693,7 +88,7 @@ static void r200Clear( GLcontext *ctx, GLbitfield mask ) +@@ -693,7 +105,7 @@ static void r200Clear( GLcontext *ctx, GLbitfield mask ) gp.param = RADEON_PARAM_LAST_CLEAR; gp.value = (int *)&clear; @@ -2656,7 +2680,7 @@ index 0741e57..c08968f 100644 DRM_RADEON_GETPARAM, &gp, sizeof(gp) ); if ( ret ) { -@@ -703,24 +98,34 @@ static void r200Clear( GLcontext *ctx, GLbitfield mask ) +@@ -703,24 +115,34 @@ static void r200Clear( GLcontext *ctx, GLbitfield mask ) /* Clear throttling needs more thought. */ @@ -2697,7 +2721,7 @@ index 0741e57..c08968f 100644 drm_radeon_clear_t clear; drm_radeon_clear_rect_t depth_boxes[RADEON_NR_SAREA_CLIPRECTS]; GLint n = 0; -@@ -755,17 +160,17 @@ static void r200Clear( GLcontext *ctx, GLbitfield mask ) +@@ -755,17 +177,17 @@ static void r200Clear( GLcontext *ctx, GLbitfield mask ) } } @@ -2720,7 +2744,7 @@ index 0741e57..c08968f 100644 for ( ; n >= 0 ; n-- ) { depth_boxes[n].f[CLEAR_X1] = (float)b[n].x1; depth_boxes[n].f[CLEAR_Y1] = (float)b[n].y1; -@@ -774,83 +179,91 @@ static void r200Clear( GLcontext *ctx, GLbitfield mask ) +@@ -774,83 +196,91 @@ static void r200Clear( GLcontext *ctx, GLbitfield mask ) depth_boxes[n].f[CLEAR_DEPTH] = ctx->Depth.Clear; } @@ -2771,7 +2795,7 @@ index 0741e57..c08968f 100644 + GLint ret; + if ( R200_DEBUG & DEBUG_IOCTL ) { -+ fprintf( stderr, "r200Clear\n"); ++ fprintf( stderr, "r200Clear %x %d\n", mask, rmesa->radeon.sarea->pfCurrentPage); + } -static void r200WaitForIdle( r200ContextPtr rmesa ) @@ -2868,7 +2892,7 @@ index 0741e57..c08968f 100644 /* This version of AllocateMemoryMESA allocates only GART memory, and * only does so after the point at which the driver has been -@@ -875,7 +288,7 @@ void *r200AllocateMemoryMESA(__DRIscreen *screen, GLsizei size, +@@ -875,7 +305,7 @@ void *r200AllocateMemoryMESA(__DRIscreen *screen, GLsizei size, fprintf(stderr, "%s sz %d %f/%f/%f\n", __FUNCTION__, size, readfreq, writefreq, priority); @@ -2877,7 +2901,7 @@ index 0741e57..c08968f 100644 return NULL; if (getenv("R200_NO_ALLOC")) -@@ -886,7 +299,7 @@ void *r200AllocateMemoryMESA(__DRIscreen *screen, GLsizei size, +@@ -886,7 +316,7 @@ void *r200AllocateMemoryMESA(__DRIscreen *screen, GLsizei size, alloc.size = size; alloc.region_offset = ®ion_offset; @@ -2886,7 +2910,7 @@ index 0741e57..c08968f 100644 DRM_RADEON_ALLOC, &alloc, sizeof(alloc)); -@@ -896,7 +309,7 @@ void *r200AllocateMemoryMESA(__DRIscreen *screen, GLsizei size, +@@ -896,7 +326,7 @@ void *r200AllocateMemoryMESA(__DRIscreen *screen, GLsizei size, } { @@ -2895,7 +2919,7 @@ index 0741e57..c08968f 100644 return (void *)(region_start + region_offset); } } -@@ -914,24 +327,24 @@ void r200FreeMemoryMESA(__DRIscreen *screen, GLvoid *pointer) +@@ -914,24 +344,24 @@ void r200FreeMemoryMESA(__DRIscreen *screen, GLvoid *pointer) if (R200_DEBUG & DEBUG_IOCTL) fprintf(stderr, "%s %p\n", __FUNCTION__, pointer); @@ -2925,7 +2949,7 @@ index 0741e57..c08968f 100644 DRM_RADEON_FREE, &memfree, sizeof(memfree)); -@@ -956,16 +369,16 @@ GLuint r200GetMemoryOffsetMESA(__DRIscreen *screen, const GLvoid *pointer) +@@ -956,16 +386,16 @@ GLuint r200GetMemoryOffsetMESA(__DRIscreen *screen, const GLvoid *pointer) card_offset = r200GartOffsetFromVirtual( rmesa, pointer ); @@ -2945,7 +2969,7 @@ index 0741e57..c08968f 100644 if (R200_DEBUG & DEBUG_IOCTL) fprintf(stderr, "r200IsGartMemory( %p ) : %d\n", pointer, valid ); -@@ -976,12 +389,12 @@ GLboolean r200IsGartMemory( r200ContextPtr rmesa, const GLvoid *pointer, +@@ -976,12 +406,12 @@ GLboolean r200IsGartMemory( r200ContextPtr rmesa, const GLvoid *pointer, GLuint r200GartOffsetFromVirtual( r200ContextPtr rmesa, const GLvoid *pointer ) { @@ -2961,7 +2985,7 @@ index 0741e57..c08968f 100644 } -@@ -989,7 +402,7 @@ GLuint r200GartOffsetFromVirtual( r200ContextPtr rmesa, const GLvoid *pointer ) +@@ -989,7 +419,7 @@ GLuint r200GartOffsetFromVirtual( r200ContextPtr rmesa, const GLvoid *pointer ) void r200InitIoctlFuncs( struct dd_function_table *functions ) { functions->Clear = r200Clear; @@ -4439,7 +4463,7 @@ index bae5644..0000000 - -#endif diff --git a/src/mesa/drivers/dri/r200/r200_state.c b/src/mesa/drivers/dri/r200/r200_state.c -index 0eaaaf6..126f78b 100644 +index 0eaaaf6..5eb61c8 100644 --- a/src/mesa/drivers/dri/r200/r200_state.c +++ b/src/mesa/drivers/dri/r200/r200_state.c @@ -47,6 +47,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. @@ -4679,7 +4703,7 @@ index 0eaaaf6..126f78b 100644 ((GLuint) (ctx->Stencil.Clear & 0xff) | (0xff << R200_STENCIL_MASK_SHIFT) | ((ctx->Stencil.WriteMask[0] & 0xff) << R200_STENCIL_WRITEMASK_SHIFT)); -@@ -1700,19 +1606,19 @@ static void r200ClearStencil( GLcontext *ctx, GLint s ) +@@ -1700,19 +1606,18 @@ static void r200ClearStencil( GLcontext *ctx, GLint s ) void r200UpdateWindow( GLcontext *ctx ) { r200ContextPtr rmesa = R200_CONTEXT(ctx); @@ -4701,11 +4725,19 @@ index 0eaaaf6..126f78b 100644 + float_ui32_type tz = { v[MAT_TZ] * rmesa->radeon.state.depth.scale }; - R200_FIREVERTICES( rmesa ); -+ radeon_firevertices(&rmesa->radeon); R200_STATECHANGE( rmesa, vpt ); rmesa->hw.vpt.cmd[VPT_SE_VPORT_XSCALE] = sx.ui32; -@@ -1744,7 +1650,7 @@ static void r200DepthRange( GLcontext *ctx, GLclampd nearval, +@@ -1733,6 +1638,8 @@ static void r200Viewport( GLcontext *ctx, GLint x, GLint y, + * values, or keep the originals hanging around. + */ + r200UpdateWindow( ctx ); ++ ++ radeon_viewport(ctx, x, y, width, height); + } + + static void r200DepthRange( GLcontext *ctx, GLclampd nearval, +@@ -1744,7 +1651,7 @@ static void r200DepthRange( GLcontext *ctx, GLclampd nearval, void r200UpdateViewportOffset( GLcontext *ctx ) { r200ContextPtr rmesa = R200_CONTEXT(ctx); @@ -4714,7 +4746,7 @@ index 0eaaaf6..126f78b 100644 GLfloat xoffset = (GLfloat)dPriv->x; GLfloat yoffset = (GLfloat)dPriv->y + dPriv->h; const GLfloat *v = ctx->Viewport._WindowMap.m; -@@ -1774,8 +1680,8 @@ void r200UpdateViewportOffset( GLcontext *ctx ) +@@ -1774,8 +1681,8 @@ void r200UpdateViewportOffset( GLcontext *ctx ) R200_STIPPLE_Y_OFFSET_MASK); /* add magic offsets, then invert */ @@ -4725,7 +4757,7 @@ index 0eaaaf6..126f78b 100644 & R200_STIPPLE_COORD_MASK); m |= ((stx << R200_STIPPLE_X_OFFSET_SHIFT) | -@@ -1788,7 +1694,7 @@ void r200UpdateViewportOffset( GLcontext *ctx ) +@@ -1788,7 +1695,7 @@ void r200UpdateViewportOffset( GLcontext *ctx ) } } @@ -4734,7 +4766,7 @@ index 0eaaaf6..126f78b 100644 } -@@ -1805,7 +1711,7 @@ static void r200ClearColor( GLcontext *ctx, const GLfloat c[4] ) +@@ -1805,7 +1712,7 @@ static void r200ClearColor( GLcontext *ctx, const GLfloat c[4] ) CLAMPED_FLOAT_TO_UBYTE(color[1], c[1]); CLAMPED_FLOAT_TO_UBYTE(color[2], c[2]); CLAMPED_FLOAT_TO_UBYTE(color[3], c[3]); @@ -4743,10 +4775,11 @@ index 0eaaaf6..126f78b 100644 color[0], color[1], color[2], color[3] ); } -@@ -1849,56 +1755,6 @@ static void r200LogicOpCode( GLcontext *ctx, GLenum opcode ) +@@ -1848,96 +1755,6 @@ static void r200LogicOpCode( GLcontext *ctx, GLenum opcode ) + rmesa->hw.msk.cmd[MSK_RB3D_ROPCNTL] = r200_rop_tab[rop]; } - +- -/* - * Set up the cliprects for either front or back-buffer drawing. - */ @@ -4797,29 +4830,49 @@ index 0eaaaf6..126f78b 100644 -} - - - static void r200DrawBuffer( GLcontext *ctx, GLenum mode ) - { - r200ContextPtr rmesa = R200_CONTEXT(ctx); -@@ -1907,7 +1763,7 @@ static void r200DrawBuffer( GLcontext *ctx, GLenum mode ) - fprintf(stderr, "%s %s\n", __FUNCTION__, - _mesa_lookup_enum_by_nr( mode )); - +-static void r200DrawBuffer( GLcontext *ctx, GLenum mode ) +-{ +- r200ContextPtr rmesa = R200_CONTEXT(ctx); +- +- if (R200_DEBUG & DEBUG_DRI) +- fprintf(stderr, "%s %s\n", __FUNCTION__, +- _mesa_lookup_enum_by_nr( mode )); +- - R200_FIREVERTICES(rmesa); /* don't pipeline cliprect changes */ -+ radeon_firevertices(&rmesa->radeon); /* don't pipeline cliprect changes */ - - if (ctx->DrawBuffer->_NumColorDrawBuffers != 1) { - /* 0 (GL_NONE) buffers or multiple color drawing buffers */ -@@ -1925,7 +1781,8 @@ static void r200DrawBuffer( GLcontext *ctx, GLenum mode ) - return; - } - +- +- if (ctx->DrawBuffer->_NumColorDrawBuffers != 1) { +- /* 0 (GL_NONE) buffers or multiple color drawing buffers */ +- FALLBACK( rmesa, R200_FALLBACK_DRAW_BUFFER, GL_TRUE ); +- return; +- } +- +- switch ( ctx->DrawBuffer->_ColorDrawBufferIndexes[0] ) { +- case BUFFER_FRONT_LEFT: +- case BUFFER_BACK_LEFT: +- FALLBACK( rmesa, R200_FALLBACK_DRAW_BUFFER, GL_FALSE ); +- break; +- default: +- FALLBACK( rmesa, R200_FALLBACK_DRAW_BUFFER, GL_TRUE ); +- return; +- } +- - r200SetCliprects( rmesa ); -+ radeonSetCliprects( &rmesa->radeon ); -+ radeonUpdatePageFlipping(&rmesa->radeon); - - /* We'll set the drawing engine's offset/pitch parameters later - * when we update other state. -@@ -2013,10 +1870,10 @@ static void r200Enable( GLcontext *ctx, GLenum cap, GLboolean state ) +- +- /* We'll set the drawing engine's offset/pitch parameters later +- * when we update other state. +- */ +-} +- +- +-static void r200ReadBuffer( GLcontext *ctx, GLenum mode ) +-{ +- /* nothing, until we implement h/w glRead/CopyPixels or CopyTexImage */ +-} +- + /* ============================================================= + * State enable/disable + */ +@@ -2013,10 +1830,10 @@ static void r200Enable( GLcontext *ctx, GLenum cap, GLboolean state ) R200_STATECHANGE(rmesa, ctx ); if ( state ) { rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_DITHER_ENABLE; @@ -4832,7 +4885,7 @@ index 0eaaaf6..126f78b 100644 } break; -@@ -2031,7 +1888,7 @@ static void r200Enable( GLcontext *ctx, GLenum cap, GLboolean state ) +@@ -2031,7 +1848,7 @@ static void r200Enable( GLcontext *ctx, GLenum cap, GLboolean state ) rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] &= ~R200_TCL_FOG_MASK; } r200UpdateSpecular( ctx ); /* for PK_SPEC */ @@ -4841,7 +4894,7 @@ index 0eaaaf6..126f78b 100644 r200ChooseVertexState( ctx ); _mesa_allow_light_in_model( ctx, !state ); break; -@@ -2068,7 +1925,7 @@ static void r200Enable( GLcontext *ctx, GLenum cap, GLboolean state ) +@@ -2068,7 +1885,7 @@ static void r200Enable( GLcontext *ctx, GLenum cap, GLboolean state ) case GL_LIGHTING: r200UpdateSpecular(ctx); /* for reflection map fixup - might set recheck_texgen for all units too */ @@ -4850,7 +4903,7 @@ index 0eaaaf6..126f78b 100644 break; case GL_LINE_SMOOTH: -@@ -2181,13 +2038,13 @@ static void r200Enable( GLcontext *ctx, GLenum cap, GLboolean state ) +@@ -2181,13 +1998,13 @@ static void r200Enable( GLcontext *ctx, GLenum cap, GLboolean state ) } case GL_SCISSOR_TEST: @@ -4868,14 +4921,25 @@ index 0eaaaf6..126f78b 100644 R200_STATECHANGE( rmesa, ctx ); if ( state ) { rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_STENCIL_ENABLE; -@@ -2443,42 +2300,99 @@ r200UpdateDrawBuffer(GLcontext *ctx) +@@ -2432,64 +2249,88 @@ static void update_texturematrix( GLcontext *ctx ) + } + } + +- +- +-/** +- * Tell the card where to render (offset, pitch). +- * Effected by glDrawBuffer, etc +- */ +-void +-r200UpdateDrawBuffer(GLcontext *ctx) ++static GLboolean r200ValidateBuffers(GLcontext *ctx) { r200ContextPtr rmesa = R200_CONTEXT(ctx); - struct gl_framebuffer *fb = ctx->DrawBuffer; +- struct gl_framebuffer *fb = ctx->DrawBuffer; - driRenderbuffer *drb; -+ struct radeon_renderbuffer *rrb; - - if (fb->_ColorDrawBufferIndexes[0] == BUFFER_FRONT_LEFT) { +- +- if (fb->_ColorDrawBufferIndexes[0] == BUFFER_FRONT_LEFT) { - /* draw to front */ - drb = (driRenderbuffer *) fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; - } @@ -4886,40 +4950,6 @@ index 0eaaaf6..126f78b 100644 - else { - /* drawing to multiple buffers, or none */ - return; -+ /* draw to front */ -+ rrb = (void *) fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; -+ } else if (fb->_ColorDrawBufferIndexes[0] == BUFFER_BACK_LEFT) { -+ /* draw to back */ -+ rrb = (void *) fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; -+ } else { -+ /* drawing to multiple buffers, or none */ -+ return; - } - -- assert(drb); -- assert(drb->flippedPitch); -+ assert(rrb); -+ assert(rrb->pitch); - - R200_STATECHANGE( rmesa, ctx ); - -+#if 0 - /* Note: we used the (possibly) page-flipped values */ - rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] -- = ((drb->flippedOffset + rmesa->r200Screen->fbLocation) -+ = ((rrb->flippedOffset + rmesa->radeon.radeonScreen->fbLocation) - & R200_COLOROFFSET_MASK); - rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = drb->flippedPitch; -- if (rmesa->sarea->tiling_enabled) { -+ if (rmesa->radeon.sarea->tiling_enabled) { - rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= R200_COLOR_TILE_ENABLE; - } -+#endif - } - -+static GLboolean r200ValidateBuffers(GLcontext *ctx) -+{ -+ r200ContextPtr rmesa = R200_CONTEXT(ctx); + struct radeon_cs_space_check bos[8]; + struct radeon_renderbuffer *rrb; + int num_bo = 0; @@ -4961,7 +4991,20 @@ index 0eaaaf6..126f78b 100644 + bos[num_bo].write_domain = 0; + bos[num_bo].new_accounted = 0; + num_bo++; -+ } + } +- +- assert(drb); +- assert(drb->flippedPitch); +- +- R200_STATECHANGE( rmesa, ctx ); +- +- /* Note: we used the (possibly) page-flipped values */ +- rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] +- = ((drb->flippedOffset + rmesa->r200Screen->fbLocation) +- & R200_COLOROFFSET_MASK); +- rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = drb->flippedPitch; +- if (rmesa->sarea->tiling_enabled) { +- rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= R200_COLOR_TILE_ENABLE; + + ret = radeon_cs_space_check(rmesa->radeon.cmdbuf.cs, bos, num_bo); + if (ret == RADEON_CS_SPACE_OP_TO_BIG) @@ -4972,10 +5015,11 @@ index 0eaaaf6..126f78b 100644 + return GL_FALSE; + flushed = 1; + goto again; -+ } + } + return GL_TRUE; -+} + } +- - -void r200ValidateState( GLcontext *ctx ) +GLboolean r200ValidateState( GLcontext *ctx ) @@ -4985,8 +5029,13 @@ index 0eaaaf6..126f78b 100644 + GLuint new_state = rmesa->radeon.NewGLState; if (new_state & (_NEW_BUFFERS | _NEW_COLOR | _NEW_PIXEL)) { - r200UpdateDrawBuffer(ctx); -@@ -2486,10 +2400,14 @@ void r200ValidateState( GLcontext *ctx ) +- r200UpdateDrawBuffer(ctx); ++ _mesa_update_framebuffer(ctx); ++ /* this updates the DrawBuffer's Width/Height if it's a FBO */ ++ _mesa_update_draw_buffer_bounds(ctx); ++ ++ R200_STATECHANGE(rmesa, ctx); + } if (new_state & (_NEW_TEXTURE | _NEW_PROGRAM)) { r200UpdateTextureState( ctx ); @@ -5002,7 +5051,7 @@ index 0eaaaf6..126f78b 100644 /* FIXME: don't really need most of these when vertex progs are enabled */ /* Need an event driven matrix update? -@@ -2533,7 +2451,8 @@ void r200ValidateState( GLcontext *ctx ) +@@ -2533,7 +2374,8 @@ void r200ValidateState( GLcontext *ctx ) else TCL_FALLBACK(ctx, R200_TCL_FALLBACK_VERTEX_PROGRAM, 0); } @@ -5012,7 +5061,7 @@ index 0eaaaf6..126f78b 100644 } -@@ -2544,7 +2463,7 @@ static void r200InvalidateState( GLcontext *ctx, GLuint new_state ) +@@ -2544,7 +2386,7 @@ static void r200InvalidateState( GLcontext *ctx, GLuint new_state ) _vbo_InvalidateState( ctx, new_state ); _tnl_InvalidateState( ctx, new_state ); _ae_invalidate_state( ctx, new_state ); @@ -5021,7 +5070,7 @@ index 0eaaaf6..126f78b 100644 } /* A hack. The r200 can actually cope just fine with materials -@@ -2573,12 +2492,13 @@ static void r200WrapRunPipeline( GLcontext *ctx ) +@@ -2573,12 +2415,13 @@ static void r200WrapRunPipeline( GLcontext *ctx ) GLboolean has_material; if (0) @@ -5038,7 +5087,18 @@ index 0eaaaf6..126f78b 100644 has_material = !ctx->VertexProgram._Enabled && ctx->Light.Enabled && check_material( ctx ); -@@ -2636,7 +2556,7 @@ void r200InitStateFuncs( struct dd_function_table *functions ) +@@ -2603,8 +2446,8 @@ void r200InitStateFuncs( struct dd_function_table *functions ) + functions->UpdateState = r200InvalidateState; + functions->LightingSpaceChange = r200LightingSpaceChange; + +- functions->DrawBuffer = r200DrawBuffer; +- functions->ReadBuffer = r200ReadBuffer; ++ functions->DrawBuffer = radeonDrawBuffer; ++ functions->ReadBuffer = radeonReadBuffer; + + functions->AlphaFunc = r200AlphaFunc; + functions->BlendColor = r200BlendColor; +@@ -2636,7 +2479,7 @@ void r200InitStateFuncs( struct dd_function_table *functions ) functions->PointParameterfv = r200PointParameter; functions->PointSize = r200PointSize; functions->RenderMode = r200RenderMode; @@ -5076,7 +5136,7 @@ index a917163..1dddbfd 100644 extern void r200LightingSpaceChange( GLcontext *ctx ); diff --git a/src/mesa/drivers/dri/r200/r200_state_init.c b/src/mesa/drivers/dri/r200/r200_state_init.c -index 9e4677e..b40690e 100644 +index 9e4677e..a71f33c 100644 --- a/src/mesa/drivers/dri/r200/r200_state_init.c +++ b/src/mesa/drivers/dri/r200/r200_state_init.c @@ -43,6 +43,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. @@ -5241,7 +5301,7 @@ index 9e4677e..b40690e 100644 return h.i; } -@@ -127,96 +243,388 @@ static int cmdscl2( int offset, int stride, int count ) +@@ -127,150 +243,480 @@ static int cmdscl2( int offset, int stride, int count ) } #define CHECK( NM, FLAG ) \ @@ -5541,10 +5601,11 @@ index 9e4677e..b40690e 100644 + atom->cmd[CTX_RB3D_ZSTENCILCNTL] |= depth_fmt; + } + ++ dwords = 10; + if (drb) -+ dwords += 4; ++ dwords += 6; + if (rrb) -+ dwords += 4; ++ dwords += 6; + + /* output the first 7 bytes of context */ + BEGIN_BATCH_NO_AUTOSTATE(dwords); @@ -5555,7 +5616,7 @@ index 9e4677e..b40690e 100644 + + if (drb) { + OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHOFFSET, 0)); -+ OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); ++ OUT_BATCH_RELOC(0, drb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); + + OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHPITCH, 0)); + OUT_BATCH(zbpitch); @@ -5571,9 +5632,7 @@ index 9e4677e..b40690e 100644 + if (rrb) { + OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLOROFFSET, 0)); + OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); -+ } + -+ if (rrb) { + OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0)); + OUT_BATCH(cbpitch); + } @@ -5592,23 +5651,80 @@ index 9e4677e..b40690e 100644 + uint32_t dwords = atom->cmd_size; + int i = atom->idx; + radeonTexObj *t = r200->state.texture.unit[i].texobj; ++ radeon_mipmap_level *lvl; + + if (t && t->mt && !t->image_override) + dwords += 2; + BEGIN_BATCH_NO_AUTOSTATE(dwords); + OUT_BATCH_TABLE(atom->cmd, 10); -+ if (t && !t->image_override) { -+ OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0, -+ RADEON_GEM_DOMAIN_VRAM, 0, 0); ++ ++ if (t && t->mt && !t->image_override) { ++ if ((ctx->Texture.Unit[i]._ReallyEnabled & TEXTURE_CUBE_BIT)) { ++ lvl = &t->mt->levels[0]; ++ OUT_BATCH_RELOC(lvl->faces[5].offset, t->mt->bo, lvl->faces[5].offset, ++ RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); ++ } else { ++ OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0, ++ RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); ++ } + } else if (!t) { + /* workaround for old CS mechanism */ + OUT_BATCH(r200->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]); -+ } else if (t->image_override) ++ } else { + OUT_BATCH(t->override_offset); ++ } + + END_BATCH(); +} + ++static void tex_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom) ++{ ++ r200ContextPtr r200 = R200_CONTEXT(ctx); ++ BATCH_LOCALS(&r200->radeon); ++ uint32_t dwords = atom->cmd_size; ++ int i = atom->idx; ++ radeonTexObj *t = r200->state.texture.unit[i].texobj; ++ radeon_mipmap_level *lvl; ++ int hastexture = 1; ++ ++ if (!t) ++ hastexture = 0; ++ else { ++ if (!t->mt && !t->bo) ++ hastexture = 0; ++ } ++ ++ dwords += 2; ++ if (hastexture) ++ dwords += 2; ++ else ++ dwords -= 2; ++ BEGIN_BATCH_NO_AUTOSTATE(dwords); ++ ++ OUT_BATCH(CP_PACKET0(R200_PP_TXFILTER_0 + (24 * i), 7)); ++ OUT_BATCH_TABLE((atom->cmd + 1), 8); ++ ++ if (hastexture) { ++ OUT_BATCH(CP_PACKET0(R200_PP_TXOFFSET_0 + (24 * i), 0)); ++ if (t->mt && !t->image_override) { ++ if ((ctx->Texture.Unit[i]._ReallyEnabled & TEXTURE_CUBE_BIT)) { ++ lvl = &t->mt->levels[0]; ++ OUT_BATCH_RELOC(lvl->faces[5].offset, t->mt->bo, lvl->faces[5].offset, ++ RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); ++ } else { ++ OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0, ++ RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); ++ } ++ } else { ++ if (t->bo) ++ OUT_BATCH_RELOC(t->tile_bits, t->bo, 0, ++ RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); ++ } ++ } ++ END_BATCH(); ++} ++ ++ +static void cube_emit(GLcontext *ctx, struct radeon_state_atom *atom) +{ + r200ContextPtr r200 = R200_CONTEXT(ctx); @@ -5639,7 +5755,9 @@ index 9e4677e..b40690e 100644 - GLcontext *ctx = rmesa->glCtx; - GLuint color_fmt, depth_fmt, i; - GLint drawPitch, drawOffset; -- ++ GLcontext *ctx = rmesa->radeon.glCtx; ++ GLuint i; + - switch ( rmesa->r200Screen->cpp ) { - case 2: - color_fmt = R200_COLOR_FORMAT_RGB565; @@ -5651,9 +5769,7 @@ index 9e4677e..b40690e 100644 - fprintf( stderr, "Error: Unsupported pixel depth... exiting\n" ); - exit( -1 ); - } -+ GLcontext *ctx = rmesa->radeon.glCtx; -+ GLuint i; - +- - rmesa->state.color.clear = 0x00000000; + rmesa->radeon.state.color.clear = 0x00000000; @@ -5672,13 +5788,15 @@ index 9e4677e..b40690e 100644 - rmesa->state.depth.scale = 1.0 / (GLfloat)0xffffff; - depth_fmt = R200_DEPTH_FORMAT_24BIT_INT_Z; - rmesa->state.stencil.clear = 0xffff0000; +- break; + default: +- fprintf( stderr, "Error: Unsupported depth %d... exiting\n", +- ctx->Visual.depthBits ); +- exit( -1 ); + rmesa->radeon.state.depth.clear = 0x00ffffff; + rmesa->radeon.state.depth.scale = 1.0 / (GLfloat)0xffffff; + rmesa->radeon.state.stencil.clear = 0xffff0000; - break; - default: - fprintf( stderr, "Error: Unsupported depth %d... exiting\n", -@@ -225,52 +633,37 @@ void r200InitState( r200ContextPtr rmesa ) ++ break; } /* Only have hw stencil when depth buffer is 24 bits deep */ @@ -5687,8 +5805,7 @@ index 9e4677e..b40690e 100644 ctx->Visual.depthBits == 24 ); - rmesa->Fallback = 0; -+ rmesa->radeon.Fallback = 0; - +- - if ( ctx->Visual.doubleBufferMode && rmesa->sarea->pfCurrentPage == 0 ) { - drawOffset = rmesa->r200Screen->backOffset; - drawPitch = rmesa->r200Screen->backPitch; @@ -5708,7 +5825,8 @@ index 9e4677e..b40690e 100644 - rmesa->state.pixel.readOffset = rmesa->state.color.drawOffset; - rmesa->state.pixel.readPitch = rmesa->state.color.drawPitch; -#endif -- ++ rmesa->radeon.Fallback = 0; + - rmesa->hw.max_state_size = 0; + rmesa->radeon.hw.max_state_size = 0; @@ -5743,7 +5861,7 @@ index 9e4677e..b40690e 100644 ALLOC_STATE( set, always, SET_STATE_SIZE, "SET/setup", 0 ); ALLOC_STATE( lin, always, LIN_STATE_SIZE, "LIN/line", 0 ); ALLOC_STATE( msk, always, MSK_STATE_SIZE, "MSK/mask", 0 ); -@@ -282,8 +675,8 @@ void r200InitState( r200ContextPtr rmesa ) +@@ -282,8 +728,8 @@ void r200InitState( r200ContextPtr rmesa ) ALLOC_STATE( cst, always, CST_STATE_SIZE, "CST/constant", 0 ); ALLOC_STATE( zbs, always, ZBS_STATE_SIZE, "ZBS/zbias", 0 ); ALLOC_STATE( tf, tf, TF_STATE_SIZE, "TF/tfactor", 0 ); @@ -5754,7 +5872,7 @@ index 9e4677e..b40690e 100644 /* make sure texture units 0/1 are emitted pair-wise for r200 t0 hang workaround */ ALLOC_STATE( tex[0], tex_pair, TEX_STATE_SIZE_NEWDRM, "TEX/tex-0", 0 ); ALLOC_STATE( tex[1], tex_pair, TEX_STATE_SIZE_NEWDRM, "TEX/tex-1", 1 ); -@@ -303,7 +696,7 @@ void r200InitState( r200ContextPtr rmesa ) +@@ -303,7 +749,7 @@ void r200InitState( r200ContextPtr rmesa ) ALLOC_STATE( afs[1], afs, AFS_STATE_SIZE, "AFS/afsinst-1", 1 ); } else { @@ -5763,14 +5881,17 @@ index 9e4677e..b40690e 100644 ALLOC_STATE( tex[0], tex_pair, TEX_STATE_SIZE_OLDDRM, "TEX/tex-0", 0 ); ALLOC_STATE( tex[1], tex_pair, TEX_STATE_SIZE_OLDDRM, "TEX/tex-1", 1 ); ALLOC_STATE( tam, tex_any, TAM_STATE_SIZE, "TAM/tam", 0 ); -@@ -321,13 +714,18 @@ void r200InitState( r200ContextPtr rmesa ) +@@ -321,13 +767,21 @@ void r200InitState( r200ContextPtr rmesa ) ALLOC_STATE( afs[0], never, AFS_STATE_SIZE, "AFS/afsinst-0", 0 ); ALLOC_STATE( afs[1], never, AFS_STATE_SIZE, "AFS/afsinst-1", 1 ); } - if (rmesa->r200Screen->drmSupportsCubeMapsR200) { + + for (i = 0; i < 5; i++) -+ rmesa->hw.tex[i].emit = tex_emit; ++ if (rmesa->radeon.radeonScreen->kernel_mm) ++ rmesa->hw.tex[i].emit = tex_emit_cs; ++ else ++ rmesa->hw.tex[i].emit = tex_emit; + if (rmesa->radeon.radeonScreen->drmSupportsCubeMapsR200) { ALLOC_STATE( cube[0], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-0", 0 ); ALLOC_STATE( cube[1], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-1", 1 ); @@ -5783,7 +5904,7 @@ index 9e4677e..b40690e 100644 } else { ALLOC_STATE( cube[0], never, CUBE_STATE_SIZE, "CUBE/tex-0", 0 ); -@@ -337,7 +735,8 @@ void r200InitState( r200ContextPtr rmesa ) +@@ -337,7 +791,8 @@ void r200InitState( r200ContextPtr rmesa ) ALLOC_STATE( cube[4], never, CUBE_STATE_SIZE, "CUBE/tex-4", 4 ); ALLOC_STATE( cube[5], never, CUBE_STATE_SIZE, "CUBE/tex-5", 5 ); } @@ -5793,7 +5914,7 @@ index 9e4677e..b40690e 100644 ALLOC_STATE( pvs, tcl_vp, PVS_STATE_SIZE, "PVS/pvscntl", 0 ); ALLOC_STATE( vpi[0], tcl_vp, VPI_STATE_SIZE, "VP/vertexprog-0", 0 ); ALLOC_STATE( vpi[1], tcl_vp_size, VPI_STATE_SIZE, "VP/vertexprog-1", 1 ); -@@ -390,13 +789,13 @@ void r200InitState( r200ContextPtr rmesa ) +@@ -390,13 +845,13 @@ void r200InitState( r200ContextPtr rmesa ) ALLOC_STATE( pix[3], texenv, PIX_STATE_SIZE, "PIX/pixstage-3", 3 ); ALLOC_STATE( pix[4], texenv, PIX_STATE_SIZE, "PIX/pixstage-4", 4 ); ALLOC_STATE( pix[5], texenv, PIX_STATE_SIZE, "PIX/pixstage-5", 5 ); @@ -5809,7 +5930,7 @@ index 9e4677e..b40690e 100644 ALLOC_STATE( spr, always, SPR_STATE_SIZE, "SPR/pointsprite", 0 ); ALLOC_STATE( ptp, tcl, PTP_STATE_SIZE, "PTP/pointparams", 0 ); } -@@ -409,87 +808,115 @@ void r200InitState( r200ContextPtr rmesa ) +@@ -409,87 +864,115 @@ void r200InitState( r200ContextPtr rmesa ) /* Fill in the packet headers: */ @@ -6005,7 +6126,7 @@ index 9e4677e..b40690e 100644 rmesa->hw.mtl[0].cmd[MTL_CMD_0] = cmdvec( R200_VS_MAT_0_EMISS, 1, 16 ); rmesa->hw.mtl[0].cmd[MTL_CMD_1] = -@@ -567,7 +994,7 @@ void r200InitState( r200ContextPtr rmesa ) +@@ -567,7 +1050,7 @@ void r200InitState( r200ContextPtr rmesa ) (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) | (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT)); @@ -6014,7 +6135,7 @@ index 9e4677e..b40690e 100644 rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCOLOR] = 0x00000000; rmesa->hw.ctx.cmd[CTX_RB3D_ABLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP | (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) | -@@ -578,18 +1005,17 @@ void r200InitState( r200ContextPtr rmesa ) +@@ -578,18 +1061,17 @@ void r200InitState( r200ContextPtr rmesa ) } rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHOFFSET] = @@ -6036,7 +6157,7 @@ index 9e4677e..b40690e 100644 R200_STENCIL_TEST_ALWAYS | R200_STENCIL_FAIL_KEEP | R200_STENCIL_ZPASS_KEEP | -@@ -599,15 +1025,14 @@ void r200InitState( r200ContextPtr rmesa ) +@@ -599,15 +1081,14 @@ void r200InitState( r200ContextPtr rmesa ) if (rmesa->using_hyperz) { rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_Z_COMPRESSION_ENABLE | R200_Z_DECOMPRESSION_ENABLE; @@ -6054,7 +6175,7 @@ index 9e4677e..b40690e 100644 case DRI_CONF_DITHER_XERRORDIFFRESET: rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_DITHER_INIT; break; -@@ -615,41 +1040,19 @@ void r200InitState( r200ContextPtr rmesa ) +@@ -615,41 +1096,19 @@ void r200InitState( r200ContextPtr rmesa ) rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_SCALE_DITHER_ENABLE; break; } @@ -6102,7 +6223,7 @@ index 9e4677e..b40690e 100644 rmesa->hw.prf.cmd[PRF_PP_PERF_CNTL] = 0; rmesa->hw.set.cmd[SET_SE_CNTL] = (R200_FFACE_CULL_CCW | -@@ -704,7 +1107,7 @@ void r200InitState( r200ContextPtr rmesa ) +@@ -704,7 +1163,7 @@ void r200InitState( r200ContextPtr rmesa ) R200_VC_NO_SWAP; #endif @@ -6111,7 +6232,7 @@ index 9e4677e..b40690e 100644 /* Bypass TCL */ rmesa->hw.cst.cmd[CST_SE_VAP_CNTL_STATUS] |= (1<<8); } -@@ -743,28 +1146,28 @@ void r200InitState( r200ContextPtr rmesa ) +@@ -743,28 +1202,28 @@ void r200InitState( r200ContextPtr rmesa ) rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT_X] = (/* R200_TEXCOORD_PROJ | */ 0x100000); /* Small default bias */ @@ -6148,7 +6269,7 @@ index 9e4677e..b40690e 100644 rmesa->hw.pix[i].cmd[PIX_PP_TXCBLEND] = (R200_TXC_ARG_A_ZERO | -@@ -967,5 +1370,7 @@ void r200InitState( r200ContextPtr rmesa ) +@@ -967,5 +1426,7 @@ void r200InitState( r200ContextPtr rmesa ) r200LightingSpaceChange( ctx ); @@ -7733,10 +7854,17 @@ index 5a4db33..19a6cad 100644 -#endif } diff --git a/src/mesa/drivers/dri/r200/r200_tex.h b/src/mesa/drivers/dri/r200/r200_tex.h -index 10ff8e8..55592ed 100644 +index 10ff8e8..886682b 100644 --- a/src/mesa/drivers/dri/r200/r200_tex.h +++ b/src/mesa/drivers/dri/r200/r200_tex.h -@@ -41,9 +41,9 @@ extern void r200SetTexOffset(__DRIcontext *pDRICtx, GLint texname, +@@ -35,15 +35,16 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + #ifndef __R200_TEX_H__ + #define __R200_TEX_H__ + ++extern void r200SetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv); + extern void r200SetTexOffset(__DRIcontext *pDRICtx, GLint texname, + unsigned long long offset, GLint depth, + GLuint pitch); extern void r200UpdateTextureState( GLcontext *ctx ); @@ -8285,10 +8413,14 @@ index 3b81ac0..0000000 - return 0; -} diff --git a/src/mesa/drivers/dri/r200/r200_texstate.c b/src/mesa/drivers/dri/r200/r200_texstate.c -index 3f9a2f4..6432068 100644 +index 3f9a2f4..4937b06 100644 --- a/src/mesa/drivers/dri/r200/r200_texstate.c +++ b/src/mesa/drivers/dri/r200/r200_texstate.c -@@ -40,6 +40,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +@@ -37,9 +37,12 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + #include "main/context.h" + #include "main/macros.h" + #include "main/texformat.h" ++#include "main/teximage.h" #include "main/texobj.h" #include "main/enums.h" @@ -8297,7 +8429,7 @@ index 3f9a2f4..6432068 100644 #include "r200_context.h" #include "r200_state.h" #include "r200_ioctl.h" -@@ -139,257 +141,6 @@ static const struct tx_table tx_table_le[] = +@@ -139,257 +142,6 @@ static const struct tx_table tx_table_le[] = #undef _ALPHA #undef _INVALID @@ -8555,7 +8687,7 @@ index 3f9a2f4..6432068 100644 /* ================================================================ * Texture combine functions */ -@@ -981,20 +732,19 @@ void r200SetTexOffset(__DRIcontext * pDRICtx, GLint texname, +@@ -981,20 +733,19 @@ void r200SetTexOffset(__DRIcontext * pDRICtx, GLint texname, { r200ContextPtr rmesa = pDRICtx->driverPrivate; struct gl_texture_object *tObj = @@ -8580,7 +8712,117 @@ index 3f9a2f4..6432068 100644 t->pp_txpitch = pitch - 32; switch (depth) { -@@ -1207,12 +957,41 @@ static GLboolean r200UpdateAllTexEnv( GLcontext *ctx ) +@@ -1014,6 +765,109 @@ void r200SetTexOffset(__DRIcontext * pDRICtx, GLint texname, + } + } + ++void r200SetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv) ++{ ++ struct gl_texture_unit *texUnit; ++ struct gl_texture_object *texObj; ++ struct gl_texture_image *texImage; ++ struct radeon_renderbuffer *rb; ++ radeon_texture_image *rImage; ++ radeonContextPtr radeon; ++ r200ContextPtr rmesa; ++ struct radeon_framebuffer *rfb; ++ radeonTexObjPtr t; ++ uint32_t pitch_val; ++ ++ target = GL_TEXTURE_RECTANGLE_ARB; ++ ++ radeon = pDRICtx->driverPrivate; ++ rmesa = pDRICtx->driverPrivate; ++ ++ rfb = dPriv->driverPrivate; ++ texUnit = &radeon->glCtx->Texture.Unit[radeon->glCtx->Texture.CurrentUnit]; ++ texObj = _mesa_select_tex_object(radeon->glCtx, texUnit, target); ++ texImage = _mesa_get_tex_image(radeon->glCtx, texObj, target, 0); ++ ++ rImage = get_radeon_texture_image(texImage); ++ t = radeon_tex_obj(texObj); ++ if (t == NULL) { ++ return; ++ } ++ ++ radeon_update_renderbuffers(pDRICtx, dPriv); ++ /* back & depth buffer are useless free them right away */ ++ rb = (void*)rfb->base.Attachment[BUFFER_DEPTH].Renderbuffer; ++ if (rb && rb->bo) { ++ radeon_bo_unref(rb->bo); ++ rb->bo = NULL; ++ } ++ rb = (void*)rfb->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer; ++ if (rb && rb->bo) { ++ radeon_bo_unref(rb->bo); ++ rb->bo = NULL; ++ } ++ rb = (void*)rfb->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer; ++ if (rb->bo == NULL) { ++ /* Failed to BO for the buffer */ ++ return; ++ } ++ ++ _mesa_lock_texture(radeon->glCtx, texObj); ++ if (t->bo) { ++ radeon_bo_unref(t->bo); ++ t->bo = NULL; ++ } ++ if (rImage->bo) { ++ radeon_bo_unref(rImage->bo); ++ rImage->bo = NULL; ++ } ++ if (t->mt) { ++ radeon_miptree_unreference(t->mt); ++ t->mt = NULL; ++ } ++ if (rImage->mt) { ++ radeon_miptree_unreference(rImage->mt); ++ rImage->mt = NULL; ++ } ++ fprintf(stderr,"settexbuf %d %dx%d@%d\n", rb->pitch, rb->width, rb->height, rb->cpp); ++ _mesa_init_teximage_fields(radeon->glCtx, target, texImage, ++ rb->width, rb->height, 1, 0, rb->cpp); ++ texImage->TexFormat = &_mesa_texformat_rgba8888_rev; ++ rImage->bo = rb->bo; ++ radeon_bo_ref(rImage->bo); ++ t->bo = rb->bo; ++ radeon_bo_ref(t->bo); ++ t->tile_bits = 0; ++ t->image_override = GL_TRUE; ++ t->override_offset = 0; ++ t->pp_txpitch &= (1 << 13) -1; ++ pitch_val = rb->pitch; ++ switch (rb->cpp) { ++ case 4: ++ t->pp_txformat = tx_table_le[MESA_FORMAT_ARGB8888].format; ++ t->pp_txfilter |= tx_table_le[MESA_FORMAT_ARGB8888].filter; ++ break; ++ case 3: ++ default: ++ t->pp_txformat = tx_table_le[MESA_FORMAT_RGB888].format; ++ t->pp_txfilter |= tx_table_le[MESA_FORMAT_RGB888].filter; ++ break; ++ case 2: ++ t->pp_txformat = tx_table_le[MESA_FORMAT_RGB565].format; ++ t->pp_txfilter |= tx_table_le[MESA_FORMAT_RGB565].filter; ++ break; ++ } ++ t->pp_txsize = ((rb->width - 1) << RADEON_TEX_USIZE_SHIFT) ++ | ((rb->height - 1) << RADEON_TEX_VSIZE_SHIFT); ++ t->pp_txformat |= R200_TXFORMAT_NON_POWER2; ++ t->pp_txpitch = pitch_val; ++ t->pp_txpitch -= 32; ++ ++ t->validated = GL_TRUE; ++ _mesa_unlock_texture(radeon->glCtx, texObj); ++ return; ++} ++ + #define REF_COLOR 1 + #define REF_ALPHA 2 + +@@ -1207,12 +1061,41 @@ static GLboolean r200UpdateAllTexEnv( GLcontext *ctx ) R200_VOLUME_FILTER_MASK) @@ -8624,7 +8866,7 @@ index 3f9a2f4..6432068 100644 R200_STATECHANGE( rmesa, tex[unit] ); -@@ -1225,36 +1004,21 @@ static void import_tex_obj_state( r200ContextPtr rmesa, +@@ -1225,36 +1108,21 @@ static void import_tex_obj_state( r200ContextPtr rmesa, cmd[TEX_PP_TXSIZE] = texobj->pp_txsize; /* NPOT only! */ cmd[TEX_PP_TXPITCH] = texobj->pp_txpitch; /* NPOT only! */ cmd[TEX_PP_BORDER_COLOR] = texobj->pp_border_color; @@ -8664,7 +8906,7 @@ index 3f9a2f4..6432068 100644 static void set_texgen_matrix( r200ContextPtr rmesa, GLuint unit, const GLfloat *s_plane, -@@ -1377,7 +1141,6 @@ static GLboolean r200_validate_texgen( GLcontext *ctx, GLuint unit ) +@@ -1377,7 +1245,6 @@ static GLboolean r200_validate_texgen( GLcontext *ctx, GLuint unit ) } else { tgcm |= R200_TEXGEN_COMP_T << (unit * 4); } @@ -8672,7 +8914,7 @@ index 3f9a2f4..6432068 100644 if (texUnit->TexGenEnabled & R_BIT) { if (texUnit->GenModeR != mode) mixed_fallback = GL_TRUE; -@@ -1513,52 +1276,6 @@ static GLboolean r200_validate_texgen( GLcontext *ctx, GLuint unit ) +@@ -1513,52 +1380,6 @@ static GLboolean r200_validate_texgen( GLcontext *ctx, GLuint unit ) return GL_TRUE; } @@ -8725,41 +8967,11 @@ index 3f9a2f4..6432068 100644 void set_re_cntl_d3d( GLcontext *ctx, int unit, GLboolean use_d3d ) { r200ContextPtr rmesa = R200_CONTEXT(ctx); -@@ -1575,237 +1292,165 @@ void set_re_cntl_d3d( GLcontext *ctx, int unit, GLboolean use_d3d ) +@@ -1575,237 +1396,169 @@ void set_re_cntl_d3d( GLcontext *ctx, int unit, GLboolean use_d3d ) } } -static GLboolean enable_tex_2d( GLcontext *ctx, int unit ) --{ -- r200ContextPtr rmesa = R200_CONTEXT(ctx); -- struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit]; -- struct gl_texture_object *tObj = texUnit->_Current; -- r200TexObjPtr t = (r200TexObjPtr) tObj->DriverData; -- -- /* Need to load the 2d images associated with this unit. -- */ -- if (t->pp_txformat & R200_TXFORMAT_NON_POWER2) { -- t->pp_txformat &= ~R200_TXFORMAT_NON_POWER2; -- t->base.dirty_images[0] = ~0; -- } -- -- ASSERT(tObj->Target == GL_TEXTURE_2D || tObj->Target == GL_TEXTURE_1D); -- -- if ( t->base.dirty_images[0] ) { -- R200_FIREVERTICES( rmesa ); -- r200SetTexImages( rmesa, tObj ); -- r200UploadTexImages( rmesa, (r200TexObjPtr) tObj->DriverData, 0 ); -- if ( !t->base.memBlock && !t->image_override ) -- return GL_FALSE; -- } -- -- set_re_cntl_d3d( ctx, unit, GL_FALSE ); -- -- return GL_TRUE; --} -- --#if ENABLE_HW_3D_TEXTURE --static GLboolean enable_tex_3d( GLcontext *ctx, int unit ) +/** + * Compute the cached hardware register values for the given texture object. + * @@ -8773,7 +8985,7 @@ index 3f9a2f4..6432068 100644 - struct gl_texture_object *tObj = texUnit->_Current; - r200TexObjPtr t = (r200TexObjPtr) tObj->DriverData; - -- /* Need to load the 3d images associated with this unit. +- /* Need to load the 2d images associated with this unit. - */ - if (t->pp_txformat & R200_TXFORMAT_NON_POWER2) { - t->pp_txformat &= ~R200_TXFORMAT_NON_POWER2; @@ -8782,12 +8994,42 @@ index 3f9a2f4..6432068 100644 + t->base.Image[0][t->mt->firstLevel]; + GLint log2Width, log2Height, log2Depth, texelBytes; + ++ if ( t->bo ) { ++ return; + } + +- ASSERT(tObj->Target == GL_TEXTURE_2D || tObj->Target == GL_TEXTURE_1D); + log2Width = firstImage->WidthLog2; + log2Height = firstImage->HeightLog2; + log2Depth = firstImage->DepthLog2; + texelBytes = firstImage->TexFormat->TexelBytes; -+ -+ + +- if ( t->base.dirty_images[0] ) { +- R200_FIREVERTICES( rmesa ); +- r200SetTexImages( rmesa, tObj ); +- r200UploadTexImages( rmesa, (r200TexObjPtr) tObj->DriverData, 0 ); +- if ( !t->base.memBlock && !t->image_override ) +- return GL_FALSE; +- } + +- set_re_cntl_d3d( ctx, unit, GL_FALSE ); +- +- return GL_TRUE; +-} +- +-#if ENABLE_HW_3D_TEXTURE +-static GLboolean enable_tex_3d( GLcontext *ctx, int unit ) +-{ +- r200ContextPtr rmesa = R200_CONTEXT(ctx); +- struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit]; +- struct gl_texture_object *tObj = texUnit->_Current; +- r200TexObjPtr t = (r200TexObjPtr) tObj->DriverData; +- +- /* Need to load the 3d images associated with this unit. +- */ +- if (t->pp_txformat & R200_TXFORMAT_NON_POWER2) { +- t->pp_txformat &= ~R200_TXFORMAT_NON_POWER2; +- t->base.dirty_images[0] = ~0; + if (!t->image_override) { + if (VALID_FORMAT(firstImage->TexFormat->MesaFormat)) { + const struct tx_table *table = _mesa_little_endian() ? tx_table_le : @@ -8960,7 +9202,8 @@ index 3f9a2f4..6432068 100644 - /* Fallback if there's a texture border */ - if ( tObj->Image[0][tObj->BaseLevel]->Border > 0 ) - return GL_FALSE; -- ++ radeonTexObj *t = radeon_tex_obj(texObj); + - /* Update state if this is a different texture object to last - * time. - */ @@ -8973,8 +9216,7 @@ index 3f9a2f4..6432068 100644 - rmesa->state.texture.unit[unit].texobj->base.bound &= - ~(1UL << unit); - } -+ radeonTexObj *t = radeon_tex_obj(texObj); - +- - rmesa->state.texture.unit[unit].texobj = t; - t->base.bound |= (1UL << unit); - t->dirty_state |= 1<hw.ctx.cmd[CTX_PP_CNTL] & (R200_TEX_0_ENABLE<hw.ctx.cmd[CTX_PP_CNTL] |= R200_TEX_0_ENABLE << unit; -+ if (!radeon_validate_texture_miptree(ctx, texObj)) -+ return GL_FALSE; - +- - R200_STATECHANGE( rmesa, vtx ); - rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_1] &= ~(7 << (unit * 3)); - rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_1] |= 4 << (unit * 3); ++ if (!radeon_validate_texture_miptree(ctx, texObj)) ++ return GL_FALSE; + +- rmesa->recheck_texgen[unit] = GL_TRUE; +- } + r200_validate_texgen(ctx, unit); + /* Configure the hardware registers (more precisely, the cached version + * of the hardware registers). */ @@ -9011,9 +9256,6 @@ index 3f9a2f4..6432068 100644 + rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_1] &= ~(7 << (unit * 3)); + rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_1] |= 4 << (unit * 3); -- rmesa->recheck_texgen[unit] = GL_TRUE; -- } -- - if (t->dirty_state & (1<hw.ctx.cmd[CTX_PP_CNTL] |= R200_TEX_1_ENABLE; if (!(rmesa->hw.cst.cmd[CST_PP_CNTL_X] & R200_PPX_TEX_1_ENABLE)) @@ -9219,10 +9461,10 @@ index 6ca9342..497b1ec 100644 ##### TARGETS ##### diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c -index c9e1dfe..cfc9785 100644 +index c9e1dfe..2c6618f 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c -@@ -44,235 +44,288 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +@@ -44,235 +44,287 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "drm.h" #include "radeon_drm.h" @@ -9600,8 +9842,7 @@ index c9e1dfe..cfc9785 100644 + r300ContextPtr r300 = R300_CONTEXT(ctx); + BATCH_LOCALS(&r300->radeon); + struct radeon_renderbuffer *rrb; -+ uint32_t zbpitch; -+ uint32_t format; ++ uint32_t format = 0; + + rrb = radeon_get_depthbuffer(&r300->radeon); + if (!rrb) @@ -9673,7 +9914,7 @@ index c9e1dfe..cfc9785 100644 cnt = r500fp_count(atom->cmd); return cnt ? (cnt * 4) + 1 : 0; } -@@ -285,8 +338,8 @@ static int check_r500fp_const(r300ContextPtr r300, struct r300_state_atom *atom) +@@ -285,8 +337,8 @@ static int check_r500fp_const(r300ContextPtr r300, struct r300_state_atom *atom) r300->hw.ATOM.idx = (IDX); \ r300->hw.ATOM.check = check_##CHK; \ r300->hw.ATOM.dirty = GL_FALSE; \ @@ -9684,7 +9925,7 @@ index c9e1dfe..cfc9785 100644 } while (0) /** * Allocate memory for the command buffer and initialize the state atom -@@ -294,7 +347,7 @@ static int check_r500fp_const(r300ContextPtr r300, struct r300_state_atom *atom) +@@ -294,7 +346,7 @@ static int check_r500fp_const(r300ContextPtr r300, struct r300_state_atom *atom) */ void r300InitCmdBuf(r300ContextPtr r300) { @@ -9693,7 +9934,7 @@ index c9e1dfe..cfc9785 100644 int has_tcl = 1; int is_r500 = 0; int i; -@@ -305,7 +358,7 @@ void r300InitCmdBuf(r300ContextPtr r300) +@@ -305,7 +357,7 @@ void r300InitCmdBuf(r300ContextPtr r300) if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) is_r500 = 1; @@ -9702,7 +9943,7 @@ index c9e1dfe..cfc9785 100644 mtu = r300->radeon.glCtx->Const.MaxTextureUnits; if (RADEON_DEBUG & DEBUG_TEXTURE) { -@@ -313,97 +366,97 @@ void r300InitCmdBuf(r300ContextPtr r300) +@@ -313,97 +365,97 @@ void r300InitCmdBuf(r300ContextPtr r300) } /* Setup the atom linked list */ @@ -9837,7 +10078,7 @@ index c9e1dfe..cfc9785 100644 for (i = 0; i < 8; i++) { r300->hw.ri.cmd[R300_RI_CMD_0 + i +1] = (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_S_SHIFT) | -@@ -412,133 +465,149 @@ void r300InitCmdBuf(r300ContextPtr r300) +@@ -412,133 +464,149 @@ void r300InitCmdBuf(r300ContextPtr r300) (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT); } ALLOC_STATE(rr, variable, R300_RR_CMDSIZE, 0); @@ -10043,7 +10284,7 @@ index c9e1dfe..cfc9785 100644 } } } -@@ -546,61 +615,39 @@ void r300InitCmdBuf(r300ContextPtr r300) +@@ -546,61 +614,39 @@ void r300InitCmdBuf(r300ContextPtr r300) /* Textures */ ALLOC_STATE(tex.filter, variable, mtu + 1, 0); r300->hw.tex.filter.cmd[R300_TEX_CMD_0] = @@ -10118,7 +10359,7 @@ index c9e1dfe..cfc9785 100644 } /** -@@ -608,68 +655,10 @@ void r300InitCmdBuf(r300ContextPtr r300) +@@ -608,68 +654,10 @@ void r300InitCmdBuf(r300ContextPtr r300) */ void r300DestroyCmdBuf(r300ContextPtr r300) { @@ -10279,7 +10520,7 @@ index a8eaa58..b7798eb 100644 #endif /* __R300_CMDBUF_H__ */ diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c -index 3743627..5d497ef 100644 +index 3743627..488fd44 100644 --- a/src/mesa/drivers/dri/r300/r300_context.c +++ b/src/mesa/drivers/dri/r300/r300_context.c @@ -44,6 +44,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. @@ -10392,7 +10633,7 @@ index 3743627..5d497ef 100644 extern struct tnl_pipeline_stage _r300_render_stage; extern const struct tnl_pipeline_stage _r300_tcl_stage; -@@ -178,6 +182,82 @@ static const struct tnl_pipeline_stage *r300_pipeline[] = { +@@ -178,6 +182,91 @@ static const struct tnl_pipeline_stage *r300_pipeline[] = { 0, }; @@ -10449,33 +10690,42 @@ index 3743627..5d497ef 100644 + +static void r300_vtbl_pre_emit_atoms(radeonContextPtr radeon) +{ -+ r300ContextPtr r300 = (r300ContextPtr)radeon; -+ BATCH_LOCALS(radeon); ++ r300ContextPtr r300 = (r300ContextPtr)radeon; ++ BATCH_LOCALS(radeon); ++ ++ r300->vap_flush_needed = GL_TRUE; ++ ++ cp_wait(radeon, R300_WAIT_3D | R300_WAIT_3D_CLEAN); ++ BEGIN_BATCH_NO_AUTOSTATE(2); ++ OUT_BATCH_REGVAL(R300_TX_INVALTAGS, R300_TX_FLUSH); ++ END_BATCH(); ++ end_3d(radeon); ++} + -+ r300->vap_flush_needed = GL_TRUE; -+ -+ cp_wait(radeon, R300_WAIT_3D | R300_WAIT_3D_CLEAN); -+ BEGIN_BATCH_NO_AUTOSTATE(2); -+ OUT_BATCH_REGVAL(R300_TX_INVALTAGS, R300_TX_FLUSH); -+ END_BATCH(); -+ end_3d(radeon); ++static void r300_fallback(GLcontext *ctx, GLuint bit, GLboolean mode) ++{ ++ r300ContextPtr r300 = R300_CONTEXT(ctx); ++ if (mode) ++ r300->radeon.Fallback |= bit; ++ else ++ r300->radeon.Fallback &= ~bit; +} + +static void r300_init_vtbl(radeonContextPtr radeon) +{ -+ radeon->vtbl.get_lock = r300_get_lock; -+ radeon->vtbl.update_viewport_offset = r300UpdateViewportOffset; -+ radeon->vtbl.update_draw_buffer = r300UpdateDrawBuffer; -+ radeon->vtbl.emit_cs_header = r300_vtbl_emit_cs_header; -+ radeon->vtbl.swtcl_flush = r300_swtcl_flush; -+ radeon->vtbl.pre_emit_atoms = r300_vtbl_pre_emit_atoms; ++ radeon->vtbl.get_lock = r300_get_lock; ++ radeon->vtbl.update_viewport_offset = r300UpdateViewportOffset; ++ radeon->vtbl.emit_cs_header = r300_vtbl_emit_cs_header; ++ radeon->vtbl.swtcl_flush = r300_swtcl_flush; ++ radeon->vtbl.pre_emit_atoms = r300_vtbl_pre_emit_atoms; ++ radeon->vtbl.fallback = r300_fallback; +} + + /* Create the device specific rendering context. */ GLboolean r300CreateContext(const __GLcontextModes * glVisual, -@@ -189,7 +269,7 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, +@@ -189,7 +278,7 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, struct dd_function_table functions; r300ContextPtr r300; GLcontext *ctx; @@ -10484,7 +10734,7 @@ index 3743627..5d497ef 100644 assert(glVisual); assert(driContextPriv); -@@ -203,13 +283,14 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, +@@ -203,13 +292,14 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, if (!(screen->chip_flags & RADEON_CHIPSET_TCL)) hw_tcl_on = future_hw_tcl_on = 0; @@ -10500,7 +10750,7 @@ index 3743627..5d497ef 100644 "def_max_anisotropy"); /* Init default driver functions then plug in our R300-specific functions -@@ -221,10 +302,6 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, +@@ -221,10 +311,6 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, r300InitTextureFuncs(&functions); r300InitShaderFuncs(&functions); @@ -10511,7 +10761,7 @@ index 3743627..5d497ef 100644 if (!radeonInitContext(&r300->radeon, &functions, glVisual, driContextPriv, sharedContextPrivate)) { -@@ -233,37 +310,10 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, +@@ -233,37 +319,10 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, } /* Init r300 context data */ @@ -10552,7 +10802,7 @@ index 3743627..5d497ef 100644 DRI_CONF_TEXTURE_DEPTH_32 : DRI_CONF_TEXTURE_DEPTH_16; /* Set the maximum texture size small enough that we can guarentee that -@@ -298,13 +348,13 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, +@@ -298,13 +357,13 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, ctx->Const.MaxLineWidth = R300_LINESIZE_MAX; ctx->Const.MaxLineWidthAA = R300_LINESIZE_MAX; @@ -10568,7 +10818,7 @@ index 3743627..5d497ef 100644 /* Initialize the software rasterizer and helper modules. */ -@@ -377,13 +427,13 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, +@@ -377,13 +436,13 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, driQueryOptionb(&r300->radeon.optionCache, "disable_lowimpact_fallback"); @@ -10584,7 +10834,7 @@ index 3743627..5d497ef 100644 tcl_mode = driQueryOptioni(&r300->radeon.optionCache, "tcl_mode"); if (driQueryOptionb(&r300->radeon.optionCache, "no_rast")) { -@@ -406,72 +456,6 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, +@@ -406,72 +465,6 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, return GL_TRUE; } @@ -10657,7 +10907,7 @@ index 3743627..5d497ef 100644 /* Destroy the device specific context. */ void r300DestroyContext(__DRIcontextPrivate * driContextPriv) -@@ -495,55 +479,27 @@ void r300DestroyContext(__DRIcontextPrivate * driContextPriv) +@@ -495,55 +488,27 @@ void r300DestroyContext(__DRIcontextPrivate * driContextPriv) assert(r300); /* should never be null */ if (r300) { @@ -11933,7 +12183,7 @@ index 4ef7f2b..8d030c6 100644 _mesa_copy_instructions(tgt, &inst, 1); diff --git a/src/mesa/drivers/dri/r300/r300_ioctl.c b/src/mesa/drivers/dri/r300/r300_ioctl.c -index ee85e22..619d268 100644 +index ee85e22..d1cf579 100644 --- a/src/mesa/drivers/dri/r300/r300_ioctl.c +++ b/src/mesa/drivers/dri/r300/r300_ioctl.c @@ -46,8 +46,9 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. @@ -12668,7 +12918,7 @@ index ee85e22..619d268 100644 { r300ContextPtr r300 = R300_CONTEXT(ctx); __DRIdrawablePrivate *dPriv = r300->radeon.dri.drawable; -+ GLframebuffer *fb = dPriv->driverPrivate; ++ struct radeon_framebuffer *rfb = dPriv->driverPrivate; + struct radeon_renderbuffer *rrb; + struct radeon_renderbuffer *rrbd; int flags = 0; @@ -12710,18 +12960,18 @@ index ee85e22..619d268 100644 + rcommonEnsureCmdBufSpace(&r300->radeon, 421 * 3, __FUNCTION__); if (flags || bits) r300EmitClearState(ctx); -+ rrbd = (void *)fb->Attachment[BUFFER_DEPTH].Renderbuffer; ++ rrbd = (void *)rfb->base.Attachment[BUFFER_DEPTH].Renderbuffer; if (flags & BUFFER_BIT_FRONT_LEFT) { - r300ClearBuffer(r300, bits | CLEARBUFFER_COLOR, swapped); -+ rrb = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; ++ rrb = (void *)rfb->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer; + r300ClearBuffer(r300, bits | CLEARBUFFER_COLOR, rrb, rrbd); bits = 0; } if (flags & BUFFER_BIT_BACK_LEFT) { - r300ClearBuffer(r300, bits | CLEARBUFFER_COLOR, swapped ^ 1); -+ rrb = (void *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; ++ rrb = (void *)rfb->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer; + r300ClearBuffer(r300, bits | CLEARBUFFER_COLOR, rrb, rrbd); bits = 0; } @@ -13744,7 +13994,7 @@ index 7c6485e..5f344be 100644 # define R500_TEX_INST_LD (1 << 22) # define R500_TEX_INST_TEXKILL (2 << 22) diff --git a/src/mesa/drivers/dri/r300/r300_render.c b/src/mesa/drivers/dri/r300/r300_render.c -index f9266e4..f46477f 100644 +index f9266e4..402d2d7 100644 --- a/src/mesa/drivers/dri/r300/r300_render.c +++ b/src/mesa/drivers/dri/r300/r300_render.c @@ -66,8 +66,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. @@ -14031,16 +14281,17 @@ index f9266e4..f46477f 100644 r300ReleaseArrays(ctx); return GL_FALSE; -@@ -347,6 +426,8 @@ static GLboolean r300RunRender(GLcontext * ctx, +@@ -347,6 +426,9 @@ static GLboolean r300RunRender(GLcontext * ctx, static int r300Fallback(GLcontext * ctx) { r300ContextPtr r300 = R300_CONTEXT(ctx); + const unsigned back = ctx->Stencil._BackFace; -+ ++ ++ FALLBACK_IF(r300->radeon.Fallback); /* Do we need to use new-style shaders? * Also is there a better way to do this? */ if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) { -@@ -371,12 +452,14 @@ static int r300Fallback(GLcontext * ctx) +@@ -371,12 +453,14 @@ static int r300Fallback(GLcontext * ctx) FALLBACK_IF(ctx->RenderMode != GL_RENDER); @@ -14061,7 +14312,7 @@ index f9266e4..f46477f 100644 if (ctx->Extensions.NV_point_sprite || ctx->Extensions.ARB_point_sprite) FALLBACK_IF(ctx->Point.PointSprite); -@@ -428,6 +511,9 @@ static GLboolean r300RunTCLRender(GLcontext * ctx, +@@ -428,6 +512,9 @@ static GLboolean r300RunTCLRender(GLcontext * ctx, return GL_TRUE; } @@ -14072,7 +14323,7 @@ index f9266e4..f46477f 100644 vp = (struct r300_vertex_program *)CURRENT_VERTEX_SHADER(ctx); diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c -index a63dbac..59728a0 100644 +index a63dbac..17e7b52 100644 --- a/src/mesa/drivers/dri/r300/r300_state.c +++ b/src/mesa/drivers/dri/r300/r300_state.c @@ -53,8 +53,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. @@ -14169,7 +14420,7 @@ index a63dbac..59728a0 100644 } /* ============================================================= -@@ -1083,10 +1066,10 @@ static void r300UpdateWindow(GLcontext * ctx) +@@ -1083,10 +1066,9 @@ static void r300UpdateWindow(GLcontext * ctx) GLfloat tx = v[MAT_TX] + xoffset + SUBPIXEL_X; GLfloat sy = -v[MAT_SY]; GLfloat ty = (-v[MAT_TY]) + yoffset + SUBPIXEL_Y; @@ -14179,63 +14430,52 @@ index a63dbac..59728a0 100644 + GLfloat tz = v[MAT_TZ] * rmesa->radeon.state.depth.scale; - R300_FIREVERTICES(rmesa); -+ radeon_firevertices(&rmesa->radeon); R300_STATECHANGE(rmesa, vpt); rmesa->hw.vpt.cmd[R300_VPT_XSCALE] = r300PackFloat32(sx); -@@ -1100,10 +1083,19 @@ static void r300UpdateWindow(GLcontext * ctx) - static void r300Viewport(GLcontext * ctx, GLint x, GLint y, - GLsizei width, GLsizei height) - { -+ r300ContextPtr rmesa = R300_CONTEXT(ctx); -+ __DRIcontext *driContext = rmesa->radeon.dri.context; - /* Don't pipeline viewport changes, conflict with window offset - * setting below. Could apply deltas to rescue pipelined viewport +@@ -1105,6 +1087,8 @@ static void r300Viewport(GLcontext * ctx, GLint x, GLint y, * values, or keep the originals hanging around. */ -+ if (rmesa->radeon.radeonScreen->driScreen->dri2.enabled) { -+ radeon_update_renderbuffers(driContext, driContext->driDrawablePriv); -+ if (driContext->driDrawablePriv != driContext->driReadablePriv) { -+ radeon_update_renderbuffers(driContext, -+ driContext->driReadablePriv); -+ } -+ } r300UpdateWindow(ctx); ++ ++ radeon_viewport(ctx, x, y, width, height); } -@@ -1144,55 +1136,25 @@ void r300UpdateViewportOffset(GLcontext * ctx) - void r300UpdateDrawBuffer(GLcontext * ctx) - { - r300ContextPtr rmesa = R300_CONTEXT(ctx); -- r300ContextPtr r300 = rmesa; - struct gl_framebuffer *fb = ctx->DrawBuffer; -- driRenderbuffer *drb; -+ struct radeon_renderbuffer *rrb; + static void r300DepthRange(GLcontext * ctx, GLclampd nearval, GLclampd farval) +@@ -1137,64 +1121,6 @@ void r300UpdateViewportOffset(GLcontext * ctx) + radeonUpdateScissor(ctx); + } - if (fb->_ColorDrawBufferIndexes[0] == BUFFER_FRONT_LEFT) { - /* draw to front */ +-/** +- * Tell the card where to render (offset, pitch). +- * Effected by glDrawBuffer, etc +- */ +-void r300UpdateDrawBuffer(GLcontext * ctx) +-{ +- r300ContextPtr rmesa = R300_CONTEXT(ctx); +- r300ContextPtr r300 = rmesa; +- struct gl_framebuffer *fb = ctx->DrawBuffer; +- driRenderbuffer *drb; +- +- if (fb->_ColorDrawBufferIndexes[0] == BUFFER_FRONT_LEFT) { +- /* draw to front */ - drb = - (driRenderbuffer *) fb->Attachment[BUFFER_FRONT_LEFT]. - Renderbuffer; -+ rrb = -+ (void *) fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; - } else if (fb->_ColorDrawBufferIndexes[0] == BUFFER_BACK_LEFT) { - /* draw to back */ +- } else if (fb->_ColorDrawBufferIndexes[0] == BUFFER_BACK_LEFT) { +- /* draw to back */ - drb = - (driRenderbuffer *) fb->Attachment[BUFFER_BACK_LEFT]. - Renderbuffer; -+ rrb = (void *) fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; - } else { - /* drawing to multiple buffers, or none */ - return; - } - +- } else { +- /* drawing to multiple buffers, or none */ +- return; +- } +- - assert(drb); - assert(drb->flippedPitch); -+ assert(rrb); -+ assert(rrb->pitch); - - R300_STATECHANGE(rmesa, cb); +- +- R300_STATECHANGE(rmesa, cb); - - r300->hw.cb.cmd[R300_CB_OFFSET] = drb->flippedOffset + //r300->radeon.state.color.drawOffset + - r300->radeon.radeonScreen->fbLocation; @@ -14262,10 +14502,12 @@ index a63dbac..59728a0 100644 - R200_COLOR_TILE_ENABLE; - } -#endif - } - +-} +- static void -@@ -1412,7 +1374,8 @@ static void r300SetupFragmentShaderTextures(GLcontext *ctx, int *tmu_mappings) + r300FetchStateParameter(GLcontext * ctx, + const gl_state_index state[STATE_LENGTH], +@@ -1412,7 +1338,8 @@ static void r300SetupFragmentShaderTextures(GLcontext *ctx, int *tmu_mappings) } r300->hw.fpt.cmd[R300_FPT_CMD_0] = @@ -14275,7 +14517,7 @@ index a63dbac..59728a0 100644 } static void r500SetupFragmentShaderTextures(GLcontext *ctx, int *tmu_mappings) -@@ -1463,7 +1426,7 @@ static GLuint translate_lod_bias(GLfloat bias) +@@ -1463,7 +1390,7 @@ static GLuint translate_lod_bias(GLfloat bias) static void r300SetupTextures(GLcontext * ctx) { int i, mtu; @@ -14284,7 +14526,7 @@ index a63dbac..59728a0 100644 r300ContextPtr r300 = R300_CONTEXT(ctx); int hw_tmu = 0; int last_hw_tmu = -1; /* -1 translates into no setup costs for fields */ -@@ -1497,21 +1460,16 @@ static void r300SetupTextures(GLcontext * ctx) +@@ -1497,21 +1424,16 @@ static void r300SetupTextures(GLcontext * ctx) /* We cannot let disabled tmu offsets pass DRM */ for (i = 0; i < mtu; i++) { if (ctx->Texture.Unit[i]._ReallyEnabled) { @@ -14309,7 +14551,7 @@ index a63dbac..59728a0 100644 } if (RADEON_DEBUG & DEBUG_STATE) -@@ -1522,29 +1480,28 @@ static void r300SetupTextures(GLcontext * ctx) +@@ -1522,29 +1444,28 @@ static void r300SetupTextures(GLcontext * ctx) r300->hw.tex.filter.cmd[R300_TEX_VALUE_0 + hw_tmu] = @@ -14348,7 +14590,7 @@ index a63dbac..59728a0 100644 WARN_ONCE("micro tiling enabled!\n"); } -@@ -1561,21 +1518,21 @@ static void r300SetupTextures(GLcontext * ctx) +@@ -1561,21 +1482,21 @@ static void r300SetupTextures(GLcontext * ctx) } r300->hw.tex.filter.cmd[R300_TEX_CMD_0] = @@ -14378,7 +14620,7 @@ index a63dbac..59728a0 100644 if (!fp) /* should only happenen once, just after context is created */ return; -@@ -1587,7 +1544,7 @@ static void r300SetupTextures(GLcontext * ctx) +@@ -1587,7 +1508,7 @@ static void r300SetupTextures(GLcontext * ctx) r300->hw.txe.cmd[R300_TXE_ENABLE] |= 1; r300->hw.tex.filter.cmd[R300_TEX_VALUE_0] = 0; r300->hw.tex.filter.cmd[R300_TEX_CMD_0] = @@ -14387,7 +14629,7 @@ index a63dbac..59728a0 100644 } r300SetupFragmentShaderTextures(ctx, tmu_mappings); } else -@@ -1756,7 +1713,7 @@ static void r300SetupRSUnit(GLcontext * ctx) +@@ -1756,7 +1677,7 @@ static void r300SetupRSUnit(GLcontext * ctx) | R300_HIRES_EN; assert(high_rr >= 0); @@ -14396,7 +14638,7 @@ index a63dbac..59728a0 100644 r300->hw.rc.cmd[2] = high_rr; if (InputsRead) -@@ -1916,7 +1873,7 @@ static void r500SetupRSUnit(GLcontext * ctx) +@@ -1916,7 +1837,7 @@ static void r500SetupRSUnit(GLcontext * ctx) | R300_HIRES_EN; assert(high_rr >= 0); @@ -14405,7 +14647,7 @@ index a63dbac..59728a0 100644 r300->hw.rc.cmd[2] = 0xC0 | high_rr; if (InputsRead) -@@ -2114,6 +2071,7 @@ static void r300SetupRealVertexProgram(r300ContextPtr rmesa) +@@ -2114,6 +2035,7 @@ static void r300SetupRealVertexProgram(r300ContextPtr rmesa) (inst_count << R300_PVS_LAST_VTX_SRC_INST_SHIFT); } @@ -14413,7 +14655,7 @@ index a63dbac..59728a0 100644 static void r300SetupVertexProgram(r300ContextPtr rmesa) { GLcontext *ctx = rmesa->radeon.glCtx; -@@ -2143,6 +2101,7 @@ static void r300SetupVertexProgram(r300ContextPtr rmesa) +@@ -2143,6 +2065,7 @@ static void r300SetupVertexProgram(r300ContextPtr rmesa) */ static void r300Enable(GLcontext * ctx, GLenum cap, GLboolean state) { @@ -14421,7 +14663,7 @@ index a63dbac..59728a0 100644 if (RADEON_DEBUG & DEBUG_STATE) fprintf(stderr, "%s( %s = %s )\n", __FUNCTION__, _mesa_lookup_enum_by_nr(cap), -@@ -2188,8 +2147,12 @@ static void r300Enable(GLcontext * ctx, GLenum cap, GLboolean state) +@@ -2188,8 +2111,12 @@ static void r300Enable(GLcontext * ctx, GLenum cap, GLboolean state) case GL_POLYGON_OFFSET_FILL: r300SetPolygonOffsetState(ctx, state); break; @@ -14435,7 +14677,7 @@ index a63dbac..59728a0 100644 break; } } -@@ -2200,6 +2163,7 @@ static void r300Enable(GLcontext * ctx, GLenum cap, GLboolean state) +@@ -2200,6 +2127,7 @@ static void r300Enable(GLcontext * ctx, GLenum cap, GLboolean state) static void r300ResetHwState(r300ContextPtr r300) { GLcontext *ctx = r300->radeon.glCtx; @@ -14443,7 +14685,15 @@ index a63dbac..59728a0 100644 int has_tcl = 1; if (!(r300->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) -@@ -2230,8 +2194,6 @@ static void r300ResetHwState(r300ContextPtr r300) +@@ -2208,6 +2136,7 @@ static void r300ResetHwState(r300ContextPtr r300) + if (RADEON_DEBUG & DEBUG_STATE) + fprintf(stderr, "%s\n", __FUNCTION__); + ++ radeon_firevertices(&r300->radeon); + r300UpdateWindow(ctx); + + r300ColorMask(ctx, +@@ -2230,8 +2159,6 @@ static void r300ResetHwState(r300ContextPtr r300) r300UpdateCulling(ctx); @@ -14452,7 +14702,7 @@ index a63dbac..59728a0 100644 r300SetBlendState(ctx); r300SetLogicOpState(ctx); -@@ -2378,20 +2340,6 @@ static void r300ResetHwState(r300ContextPtr r300) +@@ -2378,20 +2305,6 @@ static void r300ResetHwState(r300ContextPtr r300) r300BlendColor(ctx, ctx->Color.BlendColor); @@ -14473,7 +14723,7 @@ index a63dbac..59728a0 100644 r300->hw.rb3d_dither_ctl.cmd[1] = 0; r300->hw.rb3d_dither_ctl.cmd[2] = 0; r300->hw.rb3d_dither_ctl.cmd[3] = 0; -@@ -2407,12 +2355,8 @@ static void r300ResetHwState(r300ContextPtr r300) +@@ -2407,12 +2320,8 @@ static void r300ResetHwState(r300ContextPtr r300) r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[1] = 0x00000000; r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[2] = 0xffffffff; @@ -14488,7 +14738,7 @@ index a63dbac..59728a0 100644 /* XXX: Turn off when clearing buffers ? */ r300->hw.zb.cmd[R300_ZB_PITCH] |= R300_DEPTHMACROTILE_ENABLE; -@@ -2423,18 +2367,6 @@ static void r300ResetHwState(r300ContextPtr r300) +@@ -2423,18 +2332,6 @@ static void r300ResetHwState(r300ContextPtr r300) r300->hw.zb_depthclearvalue.cmd[1] = 0; @@ -14507,7 +14757,7 @@ index a63dbac..59728a0 100644 r300->hw.zstencil_format.cmd[2] = R300_ZTOP_DISABLE; r300->hw.zstencil_format.cmd[3] = 0x00000003; r300->hw.zstencil_format.cmd[4] = 0x00000000; -@@ -2455,7 +2387,7 @@ static void r300ResetHwState(r300ContextPtr r300) +@@ -2455,7 +2352,7 @@ static void r300ResetHwState(r300ContextPtr r300) r300->hw.vps.cmd[R300_VPS_ZERO_3] = 0; } @@ -14516,7 +14766,7 @@ index a63dbac..59728a0 100644 } void r300UpdateShaders(r300ContextPtr rmesa) -@@ -2466,8 +2398,8 @@ void r300UpdateShaders(r300ContextPtr rmesa) +@@ -2466,8 +2363,8 @@ void r300UpdateShaders(r300ContextPtr rmesa) ctx = rmesa->radeon.glCtx; @@ -14527,7 +14777,7 @@ index a63dbac..59728a0 100644 for (i = _TNL_FIRST_MAT; i <= _TNL_LAST_MAT; i++) { rmesa->temp_attrib[i] = -@@ -2546,10 +2478,10 @@ static void r300SetupPixelShader(r300ContextPtr rmesa) +@@ -2546,10 +2443,10 @@ static void r300SetupPixelShader(r300ContextPtr rmesa) R300_STATECHANGE(rmesa, fpi[1]); R300_STATECHANGE(rmesa, fpi[2]); R300_STATECHANGE(rmesa, fpi[3]); @@ -14542,7 +14792,7 @@ index a63dbac..59728a0 100644 for (i = 0; i < code->alu.length; i++) { rmesa->hw.fpi[0].cmd[R300_FPI_INSTR_0 + i] = code->alu.inst[i].inst0; rmesa->hw.fpi[1].cmd[R300_FPI_INSTR_0 + i] = code->alu.inst[i].inst1; -@@ -2580,7 +2512,7 @@ static void r300SetupPixelShader(r300ContextPtr rmesa) +@@ -2580,7 +2477,7 @@ static void r300SetupPixelShader(r300ContextPtr rmesa) } R300_STATECHANGE(rmesa, fpp); @@ -14551,7 +14801,7 @@ index a63dbac..59728a0 100644 for (i = 0; i < code->const_nr; i++) { const GLfloat *constant = get_fragmentprogram_constant(ctx, &fp->mesa_program.Base, code->constant[i]); -@@ -2682,7 +2614,6 @@ void r300UpdateShaderStates(r300ContextPtr rmesa) +@@ -2682,7 +2579,6 @@ void r300UpdateShaderStates(r300ContextPtr rmesa) GLcontext *ctx; ctx = rmesa->radeon.glCtx; @@ -14559,7 +14809,17 @@ index a63dbac..59728a0 100644 r300SetEarlyZState(ctx); GLuint fgdepthsrc = R300_FG_DEPTH_SRC_SCAN; -@@ -2727,7 +2658,7 @@ static void r300InvalidateState(GLcontext * ctx, GLuint new_state) +@@ -2722,12 +2618,16 @@ static void r300InvalidateState(GLcontext * ctx, GLuint new_state) + _ae_invalidate_state(ctx, new_state); + + if (new_state & (_NEW_BUFFERS | _NEW_COLOR | _NEW_PIXEL)) { +- r300UpdateDrawBuffer(ctx); ++ _mesa_update_framebuffer(ctx); ++ /* this updates the DrawBuffer's Width/Height if it's a FBO */ ++ _mesa_update_draw_buffer_bounds(ctx); ++ ++ R300_STATECHANGE(r300, cb); + } r300UpdateStateParameters(ctx, new_state); @@ -14568,7 +14828,7 @@ index a63dbac..59728a0 100644 } /** -@@ -2740,26 +2671,9 @@ void r300InitState(r300ContextPtr r300) +@@ -2740,26 +2640,9 @@ void r300InitState(r300ContextPtr r300) GLcontext *ctx = r300->radeon.glCtx; GLuint depth_fmt; @@ -14597,34 +14857,7 @@ index a63dbac..59728a0 100644 memset(&(r300->state.texture), 0, sizeof(r300->state.texture)); -@@ -2791,12 +2705,33 @@ void r300UpdateClipPlanes( GLcontext *ctx ) - } - } - -+static void r300DrawBuffer( GLcontext *ctx, GLenum mode ) -+{ -+ r300ContextPtr rmesa = R300_CONTEXT(ctx); -+ if (RADEON_DEBUG & DEBUG_DRI) -+ fprintf(stderr, "%s %s\n", __FUNCTION__, -+ _mesa_lookup_enum_by_nr( mode )); -+ -+ radeon_firevertices(&rmesa->radeon); /* don't pipeline cliprect changes */ -+ -+ radeonSetCliprects( &rmesa->radeon ); -+ if (!rmesa->radeon.radeonScreen->driScreen->dri2.enabled) -+ radeonUpdatePageFlipping(&rmesa->radeon); -+} -+ -+static void r300ReadBuffer( GLcontext *ctx, GLenum mode ) -+{ -+ if (RADEON_DEBUG & DEBUG_DRI) -+ fprintf(stderr, "%s %s\n", __FUNCTION__, -+ _mesa_lookup_enum_by_nr( mode )); -+ -+}; -+ - /** - * Initialize driver's state callback functions +@@ -2796,7 +2679,6 @@ void r300UpdateClipPlanes( GLcontext *ctx ) */ void r300InitStateFuncs(struct dd_function_table *functions) { @@ -14632,14 +14865,14 @@ index a63dbac..59728a0 100644 functions->UpdateState = r300InvalidateState; functions->AlphaFunc = r300AlphaFunc; -@@ -2833,4 +2768,8 @@ void r300InitStateFuncs(struct dd_function_table *functions) +@@ -2833,4 +2715,8 @@ void r300InitStateFuncs(struct dd_function_table *functions) functions->RenderMode = r300RenderMode; functions->ClipPlane = r300ClipPlane; + functions->Scissor = radeonScissor; + -+ functions->DrawBuffer = r300DrawBuffer; -+ functions->ReadBuffer = r300ReadBuffer; ++ functions->DrawBuffer = radeonDrawBuffer; ++ functions->ReadBuffer = radeonReadBuffer; } diff --git a/src/mesa/drivers/dri/r300/r300_state.h b/src/mesa/drivers/dri/r300/r300_state.h index 0589ab7..247a20e 100644 @@ -14682,7 +14915,7 @@ index 0589ab7..247a20e 100644 extern int future_hw_tcl_on; void _tnl_UpdateFixedFunctionProgram (GLcontext * ctx); diff --git a/src/mesa/drivers/dri/r300/r300_swtcl.c b/src/mesa/drivers/dri/r300/r300_swtcl.c -index b6e7ce1..0d8b7e5 100644 +index b6e7ce1..153582c 100644 --- a/src/mesa/drivers/dri/r300/r300_swtcl.c +++ b/src/mesa/drivers/dri/r300/r300_swtcl.c @@ -56,26 +56,23 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. @@ -14767,12 +15000,36 @@ index b6e7ce1..0d8b7e5 100644 swizzle[i][0] = SWIZZLE_ZERO; swizzle[i][1] = SWIZZLE_ZERO; swizzle[i][2] = SWIZZLE_ZERO; -@@ -215,98 +211,29 @@ static void r300SetVertexFormat( GLcontext *ctx ) - ((drm_r300_cmd_header_t *) rmesa->hw.vir[1].cmd)->packet0.count = +@@ -207,106 +203,49 @@ static void r300SetVertexFormat( GLcontext *ctx ) + } + + R300_NEWPRIM(rmesa); +- R300_STATECHANGE(rmesa, vir[0]); +- ((drm_r300_cmd_header_t *) rmesa->hw.vir[0].cmd)->packet0.count = ++ if (rmesa->radeon.radeonScreen->kernel_mm) { ++ R300_STATECHANGE(rmesa, vir[0]); ++ rmesa->hw.vir[0].cmd[0] &= 0xC000FFFF; ++ rmesa->hw.vir[1].cmd[0] &= 0xC000FFFF; ++ rmesa->hw.vir[0].cmd[0] |= ++ (r300VAPInputRoute0(&rmesa->hw.vir[0].cmd[R300_VIR_CNTL_0], ++ VB->AttribPtr, inputs, tab, nr) & 0x3FFF) << 16; ++ R300_STATECHANGE(rmesa, vir[1]); ++ rmesa->hw.vir[1].cmd[0] |= ++ (r300VAPInputRoute1(&rmesa->hw.vir[1].cmd[R300_VIR_CNTL_0], swizzle, ++ nr) & 0x3FFF) << 16; ++ } else { ++ R300_STATECHANGE(rmesa, vir[0]); ++ ((drm_r300_cmd_header_t *) rmesa->hw.vir[0].cmd)->packet0.count = + r300VAPInputRoute0(&rmesa->hw.vir[0].cmd[R300_VIR_CNTL_0], + VB->AttribPtr, inputs, tab, nr); +- R300_STATECHANGE(rmesa, vir[1]); +- ((drm_r300_cmd_header_t *) rmesa->hw.vir[1].cmd)->packet0.count = ++ R300_STATECHANGE(rmesa, vir[1]); ++ ((drm_r300_cmd_header_t *) rmesa->hw.vir[1].cmd)->packet0.count = r300VAPInputRoute1(&rmesa->hw.vir[1].cmd[R300_VIR_CNTL_0], swizzle, nr); - -+ ++ } R300_STATECHANGE(rmesa, vic); rmesa->hw.vic.cmd[R300_VIC_CNTL_0] = r300VAPInputCntl0(ctx, InputsRead); rmesa->hw.vic.cmd[R300_VIC_CNTL_1] = r300VAPInputCntl1(ctx, InputsRead); @@ -14875,7 +15132,7 @@ index b6e7ce1..0d8b7e5 100644 } static GLuint reduced_prim[] = { -@@ -346,13 +273,13 @@ static void r300RenderPrimitive( GLcontext *ctx, GLenum prim ); +@@ -346,13 +285,13 @@ static void r300RenderPrimitive( GLcontext *ctx, GLenum prim ); #undef LOCAL_VARS #undef ALLOC_VERTS #define CTX_ARG r300ContextPtr rmesa @@ -14893,7 +15150,7 @@ index b6e7ce1..0d8b7e5 100644 #define DO_DEBUG_VERTS (1 && (RADEON_DEBUG & DEBUG_VERTS)) #define PRINT_VERTEX(x) #undef TAG -@@ -409,7 +336,7 @@ static struct { +@@ -409,7 +348,7 @@ static struct { #define VERT_Y(_v) _v->v.y #define VERT_Z(_v) _v->v.z #define AREA_IS_CCW( a ) (a < 0) @@ -14902,7 +15159,7 @@ index b6e7ce1..0d8b7e5 100644 /* Only used to pull back colors into vertices (ie, we know color is * floating point). -@@ -455,7 +382,7 @@ do { \ +@@ -455,7 +394,7 @@ do { \ ***********************************************************************/ #define RASTERIZE(x) r300RasterPrimitive( ctx, reduced_prim[x] ) @@ -14911,7 +15168,7 @@ index b6e7ce1..0d8b7e5 100644 #undef TAG #define TAG(x) x #include "tnl_dd/t_dd_unfilled.h" -@@ -512,8 +439,8 @@ static void init_rast_tab( void ) +@@ -512,8 +451,8 @@ static void init_rast_tab( void ) #undef LOCAL_VARS #define LOCAL_VARS \ r300ContextPtr rmesa = R300_CONTEXT(ctx); \ @@ -14922,7 +15179,7 @@ index b6e7ce1..0d8b7e5 100644 const GLuint * const elt = TNL_CONTEXT(ctx)->vb.Elts; \ const GLboolean stipple = ctx->Line.StippleFlag; \ (void) elt; (void) stipple; -@@ -545,7 +472,7 @@ static void r300ChooseRenderState( GLcontext *ctx ) +@@ -545,7 +484,7 @@ static void r300ChooseRenderState( GLcontext *ctx ) if (flags & DD_TRI_LIGHT_TWOSIDE) index |= R300_TWOSIDE_BIT; if (flags & DD_TRI_UNFILLED) index |= R300_UNFILLED_BIT; @@ -14931,7 +15188,7 @@ index b6e7ce1..0d8b7e5 100644 tnl->Driver.Render.Points = rast_tab[index].points; tnl->Driver.Render.Line = rast_tab[index].line; tnl->Driver.Render.ClippedLine = rast_tab[index].line; -@@ -562,7 +489,7 @@ static void r300ChooseRenderState( GLcontext *ctx ) +@@ -562,7 +501,7 @@ static void r300ChooseRenderState( GLcontext *ctx ) tnl->Driver.Render.ClippedPolygon = _tnl_RenderClippedPolygon; } @@ -14940,7 +15197,7 @@ index b6e7ce1..0d8b7e5 100644 } } -@@ -572,18 +499,18 @@ static void r300RenderStart(GLcontext *ctx) +@@ -572,18 +511,18 @@ static void r300RenderStart(GLcontext *ctx) r300ContextPtr rmesa = R300_CONTEXT( ctx ); // fprintf(stderr, "%s\n", __FUNCTION__); @@ -14965,7 +15222,7 @@ index b6e7ce1..0d8b7e5 100644 } static void r300RenderFinish(GLcontext *ctx) -@@ -593,10 +520,10 @@ static void r300RenderFinish(GLcontext *ctx) +@@ -593,10 +532,10 @@ static void r300RenderFinish(GLcontext *ctx) static void r300RasterPrimitive( GLcontext *ctx, GLuint hwprim ) { r300ContextPtr rmesa = R300_CONTEXT(ctx); @@ -14979,7 +15236,7 @@ index b6e7ce1..0d8b7e5 100644 } } -@@ -604,14 +531,14 @@ static void r300RenderPrimitive(GLcontext *ctx, GLenum prim) +@@ -604,14 +543,14 @@ static void r300RenderPrimitive(GLcontext *ctx, GLenum prim) { r300ContextPtr rmesa = R300_CONTEXT(ctx); @@ -14996,7 +15253,7 @@ index b6e7ce1..0d8b7e5 100644 } static void r300ResetLineStipple(GLcontext *ctx) -@@ -625,12 +552,12 @@ void r300InitSwtcl(GLcontext *ctx) +@@ -625,12 +564,12 @@ void r300InitSwtcl(GLcontext *ctx) TNLcontext *tnl = TNL_CONTEXT(ctx); r300ContextPtr rmesa = R300_CONTEXT(ctx); static int firsttime = 1; @@ -15011,7 +15268,7 @@ index b6e7ce1..0d8b7e5 100644 tnl->Driver.Render.Start = r300RenderStart; tnl->Driver.Render.Finish = r300RenderFinish; tnl->Driver.Render.PrimitiveNotify = r300RenderPrimitive; -@@ -638,15 +565,15 @@ void r300InitSwtcl(GLcontext *ctx) +@@ -638,15 +577,15 @@ void r300InitSwtcl(GLcontext *ctx) tnl->Driver.Render.BuildVertices = _tnl_build_vertices; tnl->Driver.Render.CopyPV = _tnl_copy_pv; tnl->Driver.Render.Interp = _tnl_interp; @@ -15034,7 +15291,7 @@ index b6e7ce1..0d8b7e5 100644 _tnl_invalidate_vertex_state( ctx, ~0 ); _tnl_invalidate_vertices( ctx, ~0 ); -@@ -655,9 +582,9 @@ void r300InitSwtcl(GLcontext *ctx) +@@ -655,9 +594,9 @@ void r300InitSwtcl(GLcontext *ctx) _tnl_need_projected_coords( ctx, GL_FALSE ); r300ChooseRenderState(ctx); @@ -15046,7 +15303,7 @@ index b6e7ce1..0d8b7e5 100644 _mesa_validate_all_lighting_tables; } -@@ -665,33 +592,53 @@ void r300DestroySwtcl(GLcontext *ctx) +@@ -665,33 +604,53 @@ void r300DestroySwtcl(GLcontext *ctx) { } @@ -16739,7 +16996,7 @@ index b03eefa..0000000 - return 0; -} diff --git a/src/mesa/drivers/dri/r300/r300_texstate.c b/src/mesa/drivers/dri/r300/r300_texstate.c -index e2329f0..8a90069 100644 +index e2329f0..2d7f392 100644 --- a/src/mesa/drivers/dri/r300/r300_texstate.c +++ b/src/mesa/drivers/dri/r300/r300_texstate.c @@ -47,7 +47,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. @@ -17368,7 +17625,7 @@ index e2329f0..8a90069 100644 + radeon_texture_image *rImage; + radeonContextPtr radeon; + r300ContextPtr rmesa; -+ GLframebuffer *fb; ++ struct radeon_framebuffer *rfb; + radeonTexObjPtr t; + uint32_t pitch_val; @@ -17386,7 +17643,7 @@ index e2329f0..8a90069 100644 + radeon = pDRICtx->driverPrivate; + rmesa = pDRICtx->driverPrivate; + -+ fb = dPriv->driverPrivate; ++ rfb = dPriv->driverPrivate; + texUnit = &radeon->glCtx->Texture.Unit[radeon->glCtx->Texture.CurrentUnit]; + texObj = _mesa_select_tex_object(radeon->glCtx, texUnit, target); + texImage = _mesa_get_tex_image(radeon->glCtx, texObj, target, 0); @@ -17399,17 +17656,17 @@ index e2329f0..8a90069 100644 + + radeon_update_renderbuffers(pDRICtx, dPriv); + /* back & depth buffer are useless free them right away */ -+ rb = (void*)fb->Attachment[BUFFER_DEPTH].Renderbuffer; ++ rb = (void*)rfb->base.Attachment[BUFFER_DEPTH].Renderbuffer; + if (rb && rb->bo) { + radeon_bo_unref(rb->bo); + rb->bo = NULL; + } -+ rb = (void*)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; ++ rb = (void*)rfb->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer; + if (rb && rb->bo) { + radeon_bo_unref(rb->bo); + rb->bo = NULL; + } -+ rb = (void*)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; ++ rb = (void*)rfb->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer; + if (rb->bo == NULL) { + /* Failed to BO for the buffer */ + return; @@ -18501,7 +18758,7 @@ index 3add775..0000000 -#endif /* __RADEON_IOCTL_H__ */ diff --git a/src/mesa/drivers/dri/r300/radeon_lock.c b/src/mesa/drivers/dri/r300/radeon_lock.c deleted file mode 100644 -index 4f47afd..af4108a +index 4f47afd..0000000 --- a/src/mesa/drivers/dri/r300/radeon_lock.c +++ /dev/null @@ -1,137 +0,0 @@ @@ -18644,7 +18901,7 @@ index 4f47afd..af4108a -} diff --git a/src/mesa/drivers/dri/r300/radeon_lock.h b/src/mesa/drivers/dri/r300/radeon_lock.h deleted file mode 100644 -index a344837..64bdf94 +index a344837..0000000 --- a/src/mesa/drivers/dri/r300/radeon_lock.h +++ /dev/null @@ -1,115 +0,0 @@ @@ -18778,7 +19035,7 @@ index 58bc0d5..8a945d8 100644 diff --git a/src/mesa/drivers/dri/r300/radeon_span.c b/src/mesa/drivers/dri/r300/radeon_span.c deleted file mode 100644 -index 16f9fb9..232868c +index 16f9fb9..0000000 --- a/src/mesa/drivers/dri/r300/radeon_span.c +++ /dev/null @@ -1,349 +0,0 @@ @@ -20629,28 +20886,6 @@ index 0000000..f80f0f7 +#include "radeon_cs_legacy.h" + +#endif -diff --git a/src/mesa/drivers/dri/radeon/radeon_chipset.h b/src/mesa/drivers/dri/radeon/radeon_chipset.h -index f6bd1eb..55a73ea 100644 ---- a/src/mesa/drivers/dri/radeon/radeon_chipset.h -+++ b/src/mesa/drivers/dri/radeon/radeon_chipset.h -@@ -247,9 +247,6 @@ - #define PCI_CHIP_RS350_7835 0x7835 - #define PCI_CHIP_RS690_791E 0x791E - #define PCI_CHIP_RS690_791F 0x791F --#define PCI_CHIP_RS600_793F 0x793F --#define PCI_CHIP_RS600_7941 0x7941 --#define PCI_CHIP_RS600_7942 0x7942 - #define PCI_CHIP_RS740_796C 0x796C - #define PCI_CHIP_RS740_796D 0x796D - #define PCI_CHIP_RS740_796E 0x796E -@@ -273,7 +270,6 @@ enum { - CHIP_FAMILY_R420, - CHIP_FAMILY_RV410, - CHIP_FAMILY_RS400, -- CHIP_FAMILY_RS600, - CHIP_FAMILY_RS690, - CHIP_FAMILY_RS740, - CHIP_FAMILY_RV515, diff --git a/src/mesa/drivers/dri/radeon/radeon_cmdbuf.h b/src/mesa/drivers/dri/radeon/radeon_cmdbuf.h new file mode 100644 index 0000000..4b5116c @@ -20802,10 +21037,10 @@ index 0000000..4b5116c +#endif diff --git a/src/mesa/drivers/dri/radeon/radeon_common.c b/src/mesa/drivers/dri/radeon/radeon_common.c new file mode 100644 -index 0000000..f7c0d7d +index 0000000..99270c9 --- /dev/null +++ b/src/mesa/drivers/dri/radeon/radeon_common.c -@@ -0,0 +1,849 @@ +@@ -0,0 +1,1104 @@ +/************************************************************************** + +Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. @@ -20859,7 +21094,7 @@ index 0000000..f7c0d7d +#include "main/light.h" +#include "main/framebuffer.h" +#include "main/simple_list.h" -+ ++#include "main/renderbuffer.h" +#include "swrast/swrast.h" +#include "vbo/vbo.h" +#include "tnl/tnl.h" @@ -20940,6 +21175,38 @@ index 0000000..f7c0d7d + } +} + ++static void radeon_get_cliprects(radeonContextPtr radeon, ++ struct drm_clip_rect **cliprects, ++ unsigned int *num_cliprects, ++ int *x_off, int *y_off) ++{ ++ __DRIdrawablePrivate *dPriv = radeon->dri.drawable; ++ struct radeon_framebuffer *rfb = dPriv->driverPrivate; ++ ++ if (radeon->constant_cliprect) { ++ radeon->fboRect.x1 = 0; ++ radeon->fboRect.y1 = 0; ++ radeon->fboRect.x2 = radeon->glCtx->DrawBuffer->Width; ++ radeon->fboRect.y2 = radeon->glCtx->DrawBuffer->Height; ++ ++ *cliprects = &radeon->fboRect; ++ *num_cliprects = 1; ++ *x_off = 0; ++ *y_off = 0; ++ } else if (radeon->front_cliprects || ++ rfb->pf_active || dPriv->numBackClipRects == 0) { ++ *cliprects = dPriv->pClipRects; ++ *num_cliprects = dPriv->numClipRects; ++ *x_off = dPriv->x; ++ *y_off = dPriv->y; ++ } else { ++ *num_cliprects = dPriv->numBackClipRects; ++ *cliprects = dPriv->pBackClipRects; ++ *x_off = dPriv->backX; ++ *y_off = dPriv->backY; ++ } ++} ++ +/** + * Update cliprects and scissors. + */ @@ -20947,49 +21214,36 @@ index 0000000..f7c0d7d +{ + __DRIdrawablePrivate *const drawable = radeon->dri.drawable; + __DRIdrawablePrivate *const readable = radeon->dri.readable; -+ GLframebuffer *const draw_fb = (GLframebuffer*)drawable->driverPrivate; -+ GLframebuffer *const read_fb = (GLframebuffer*)readable->driverPrivate; ++ struct radeon_framebuffer *const draw_rfb = drawable->driverPrivate; ++ struct radeon_framebuffer *const read_rfb = readable->driverPrivate; ++ int x_off, y_off; + -+ if (!radeon->radeonScreen->driScreen->dri2.enabled) { -+ if (draw_fb->_ColorDrawBufferIndexes[0] == BUFFER_BACK_LEFT) { -+ /* Can't ignore 2d windows if we are page flipping. */ -+ if (drawable->numBackClipRects == 0 || radeon->doPageFlip || -+ radeon->sarea->pfCurrentPage == 1) { -+ radeon->numClipRects = drawable->numClipRects; -+ radeon->pClipRects = drawable->pClipRects; -+ } else { -+ radeon->numClipRects = drawable->numBackClipRects; -+ radeon->pClipRects = drawable->pBackClipRects; -+ } -+ } else { -+ /* front buffer (or none, or multiple buffers */ -+ radeon->numClipRects = drawable->numClipRects; -+ radeon->pClipRects = drawable->pClipRects; -+ } -+ } ++ radeon_get_cliprects(radeon, &radeon->pClipRects, ++ &radeon->numClipRects, &x_off, &y_off); + -+ if ((draw_fb->Width != drawable->w) || -+ (draw_fb->Height != drawable->h)) { -+ _mesa_resize_framebuffer(radeon->glCtx, draw_fb, ++ if ((draw_rfb->base.Width != drawable->w) || ++ (draw_rfb->base.Height != drawable->h)) { ++ _mesa_resize_framebuffer(radeon->glCtx, &draw_rfb->base, + drawable->w, drawable->h); -+ draw_fb->Initialized = GL_TRUE; ++ draw_rfb->base.Initialized = GL_TRUE; + } + + if (drawable != readable) { -+ if ((read_fb->Width != readable->w) || -+ (read_fb->Height != readable->h)) { -+ _mesa_resize_framebuffer(radeon->glCtx, read_fb, ++ if ((read_rfb->base.Width != readable->w) || ++ (read_rfb->base.Height != readable->h)) { ++ _mesa_resize_framebuffer(radeon->glCtx, &read_rfb->base, + readable->w, readable->h); -+ read_fb->Initialized = GL_TRUE; ++ read_rfb->base.Initialized = GL_TRUE; + } + } + + if (radeon->state.scissor.enabled) + radeonRecalcScissorRects(radeon); + -+ radeon->lastStamp = drawable->lastStamp; +} + ++ ++ +void radeonUpdateScissor( GLcontext *ctx ) +{ + radeonContextPtr rmesa = RADEON_CONTEXT(ctx); @@ -21156,6 +21410,37 @@ index 0000000..f7c0d7d + UNLOCK_HARDWARE(radeon); +} + ++static void radeon_flip_renderbuffers(struct radeon_framebuffer *rfb) ++{ ++ int current_page = rfb->pf_current_page; ++ int next_page = (current_page + 1) % rfb->pf_num_pages; ++ struct gl_renderbuffer *tmp_rb; ++ ++ /* Exchange renderbuffers if necessary but make sure their ++ * reference counts are preserved. ++ */ ++ if (rfb->color_rb[current_page] && ++ rfb->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer != ++ &rfb->color_rb[current_page]->base) { ++ tmp_rb = NULL; ++ _mesa_reference_renderbuffer(&tmp_rb, ++ rfb->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer); ++ tmp_rb = &rfb->color_rb[current_page]->base; ++ _mesa_reference_renderbuffer(&rfb->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer, tmp_rb); ++ _mesa_reference_renderbuffer(&tmp_rb, NULL); ++ } ++ ++ if (rfb->color_rb[next_page] && ++ rfb->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer != ++ &rfb->color_rb[next_page]->base) { ++ tmp_rb = NULL; ++ _mesa_reference_renderbuffer(&tmp_rb, ++ rfb->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer); ++ tmp_rb = &rfb->color_rb[next_page]->base; ++ _mesa_reference_renderbuffer(&rfb->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer, tmp_rb); ++ _mesa_reference_renderbuffer(&tmp_rb, NULL); ++ } ++} + +/* Copy the back color buffer to the front color buffer. + */ @@ -21163,10 +21448,8 @@ index 0000000..f7c0d7d + const drm_clip_rect_t *rect) +{ + radeonContextPtr rmesa; ++ struct radeon_framebuffer *rfb; + GLint nbox, i, ret; -+ GLboolean missed_target; -+ int64_t ust; -+ __DRIscreenPrivate *psp; + + assert(dPriv); + assert(dPriv->driContextPriv); @@ -21174,24 +21457,12 @@ index 0000000..f7c0d7d + + rmesa = (radeonContextPtr) dPriv->driContextPriv->driverPrivate; + ++ rfb = dPriv->driverPrivate; ++ + if ( RADEON_DEBUG & DEBUG_IOCTL ) { + fprintf( stderr, "\n%s( %p )\n\n", __FUNCTION__, (void *) rmesa->glCtx ); + } + -+ radeon_firevertices(rmesa); -+ LOCK_HARDWARE( rmesa ); -+ -+ /* Throttle the frame rate -- only allow one pending swap buffers -+ * request at a time. -+ */ -+ radeonWaitForFrameCompletion( rmesa ); -+ if (!rect) -+ { -+ UNLOCK_HARDWARE( rmesa ); -+ driWaitForVBlank( dPriv, & missed_target ); -+ LOCK_HARDWARE( rmesa ); -+ } -+ + nbox = dPriv->numClipRects; /* must be in locked region */ + + for ( i = 0 ; i < nbox ; ) { @@ -21237,45 +21508,13 @@ index 0000000..f7c0d7d + } + + UNLOCK_HARDWARE( rmesa ); -+ if (!rect) -+ { -+ psp = dPriv->driScreenPriv; -+ rmesa->swap_count++; -+ (*psp->systemTime->getUST)( & ust ); -+ if ( missed_target ) { -+ rmesa->swap_missed_count++; -+ rmesa->swap_missed_ust = ust - rmesa->swap_ust; -+ } -+ -+ rmesa->swap_ust = ust; -+ rmesa->hw.all_dirty = GL_TRUE; -+ -+ } +} + -+void radeonPageFlip( __DRIdrawablePrivate *dPriv ) ++static int radeonScheduleSwap(__DRIdrawablePrivate *dPriv, GLboolean *missed_target) +{ + radeonContextPtr rmesa; -+ GLint ret; -+ GLboolean missed_target; -+ __DRIscreenPrivate *psp; -+ struct radeon_renderbuffer *rrb; -+ GLframebuffer *fb = dPriv->driverPrivate; -+ -+ assert(dPriv); -+ assert(dPriv->driContextPriv); -+ assert(dPriv->driContextPriv->driverPrivate); + + rmesa = (radeonContextPtr) dPriv->driContextPriv->driverPrivate; -+ rrb = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; -+ -+ psp = dPriv->driScreenPriv; -+ -+ if ( RADEON_DEBUG & DEBUG_IOCTL ) { -+ fprintf(stderr, "%s: pfCurrentPage: %d\n", __FUNCTION__, -+ rmesa->sarea->pfCurrentPage); -+ } -+ + radeon_firevertices(rmesa); + + LOCK_HARDWARE( rmesa ); @@ -21283,48 +21522,62 @@ index 0000000..f7c0d7d + if (!dPriv->numClipRects) { + UNLOCK_HARDWARE(rmesa); + usleep(10000); /* throttle invisible client 10ms */ -+ return; ++ return 0; + } + ++ radeonWaitForFrameCompletion(rmesa); ++ ++ UNLOCK_HARDWARE(rmesa); ++ driWaitForVBlank(dPriv, missed_target); ++ LOCK_HARDWARE(rmesa); ++ ++ return 0; ++} ++ ++static GLboolean radeonPageFlip( __DRIdrawablePrivate *dPriv ) ++{ ++ radeonContextPtr radeon; ++ GLint ret; ++ __DRIscreenPrivate *psp; ++ struct radeon_renderbuffer *rrb; ++ struct radeon_framebuffer *rfb; ++ ++ assert(dPriv); ++ assert(dPriv->driContextPriv); ++ assert(dPriv->driContextPriv->driverPrivate); ++ ++ radeon = (radeonContextPtr) dPriv->driContextPriv->driverPrivate; ++ rfb = dPriv->driverPrivate; ++ rrb = (void *)rfb->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer; ++ ++ psp = dPriv->driScreenPriv; ++ ++ if ( RADEON_DEBUG & DEBUG_IOCTL ) { ++ fprintf(stderr, "%s: pfCurrentPage: %d %d\n", __FUNCTION__, ++ radeon->sarea->pfCurrentPage, radeon->sarea->pfState); ++ } + drm_clip_rect_t *box = dPriv->pClipRects; -+ drm_clip_rect_t *b = rmesa->sarea->boxes; ++ drm_clip_rect_t *b = radeon->sarea->boxes; + b[0] = box[0]; -+ rmesa->sarea->nbox = 1; ++ radeon->sarea->nbox = 1; + -+ /* Throttle the frame rate -- only allow a few pending swap buffers -+ * request at a time. -+ */ -+ radeonWaitForFrameCompletion( rmesa ); -+ UNLOCK_HARDWARE( rmesa ); -+ driWaitForVBlank( dPriv, & missed_target ); -+ if ( missed_target ) { -+ rmesa->swap_missed_count++; -+ (void) (*psp->systemTime->getUST)( & rmesa->swap_missed_ust ); -+ } -+ LOCK_HARDWARE( rmesa ); -+ -+ ret = drmCommandNone( rmesa->dri.fd, DRM_RADEON_FLIP ); ++ ret = drmCommandNone( radeon->dri.fd, DRM_RADEON_FLIP ); + -+ UNLOCK_HARDWARE( rmesa ); ++ UNLOCK_HARDWARE( radeon ); + + if ( ret ) { + fprintf( stderr, "DRM_RADEON_FLIP: return = %d\n", ret ); -+ exit( 1 ); ++ return GL_FALSE; + } + -+ rmesa->swap_count++; -+ (void) (*psp->systemTime->getUST)( & rmesa->swap_ust ); -+ -+ /* Get ready for drawing next frame. Update the renderbuffers' -+ * flippedOffset/Pitch fields so we draw into the right place. -+ */ -+ // driFlipRenderbuffers(rmesa->glCtx->WinSysDrawBuffer, -+ // rmesa->sarea->pfCurrentPage); -+ -+ rmesa->state.color.rrb = rrb; ++ if (!rfb->pf_active) ++ return GL_FALSE; + -+ if (rmesa->vtbl.update_draw_buffer) -+ rmesa->vtbl.update_draw_buffer(rmesa->glCtx); ++ rfb->pf_current_page = radeon->sarea->pfCurrentPage; ++ radeon_flip_renderbuffers(rfb); ++ radeon_draw_buffer(radeon->glCtx, &rfb->base); ++ ++ return GL_TRUE; +} + + @@ -21333,6 +21586,9 @@ index 0000000..f7c0d7d + */ +void radeonSwapBuffers(__DRIdrawablePrivate * dPriv) +{ ++ int64_t ust; ++ __DRIscreenPrivate *psp; ++ + if (dPriv->driContextPriv && dPriv->driContextPriv->driverPrivate) { + radeonContextPtr radeon; + GLcontext *ctx; @@ -21341,12 +21597,29 @@ index 0000000..f7c0d7d + ctx = radeon->glCtx; + + if (ctx->Visual.doubleBufferMode) { ++ GLboolean missed_target; ++ struct radeon_framebuffer *rfb = dPriv->driverPrivate; + _mesa_notifySwapBuffers(ctx);/* flush pending rendering comands */ -+ if (radeon->doPageFlip) { ++ ++ radeonScheduleSwap(dPriv, &missed_target); ++ ++ if (rfb->pf_active) { + radeonPageFlip(dPriv); + } else { + radeonCopyBuffer(dPriv, NULL); + } ++ ++ psp = dPriv->driScreenPriv; ++ ++ rfb->swap_count++; ++ (*psp->systemTime->getUST)( & ust ); ++ if ( missed_target ) { ++ rfb->swap_missed_count++; ++ rfb->swap_missed_ust = ust - rfb->swap_ust; ++ } ++ ++ rfb->swap_ust = ust; ++ radeon->hw.all_dirty = GL_TRUE; + } + } else { + /* XXX this shouldn't be an error but we can't handle it for now */ @@ -21381,7 +21654,224 @@ index 0000000..f7c0d7d + } +} + ++void radeon_draw_buffer(GLcontext *ctx, struct gl_framebuffer *fb) ++{ ++ radeonContextPtr radeon = RADEON_CONTEXT(ctx); ++ struct radeon_renderbuffer *rrbDepth = NULL, *rrbStencil = NULL, ++ *rrbColor = NULL; ++ + ++ if (!fb) { ++ /* this can happen during the initial context initialization */ ++ return; ++ } ++ ++ /* radeons only handle 1 color draw so far */ ++ if (fb->_NumColorDrawBuffers != 1) { ++ radeon->vtbl.fallback(ctx, RADEON_FALLBACK_DRAW_BUFFER, GL_TRUE); ++ return; ++ } ++ ++ /* Do this here, note core Mesa, since this function is called from ++ * many places within the driver. ++ */ ++ if (ctx->NewState & (_NEW_BUFFERS | _NEW_COLOR | _NEW_PIXEL)) { ++ /* this updates the DrawBuffer->_NumColorDrawBuffers fields, etc */ ++ _mesa_update_framebuffer(ctx); ++ /* this updates the DrawBuffer's Width/Height if it's a FBO */ ++ _mesa_update_draw_buffer_bounds(ctx); ++ } ++ ++ if (fb->_Status != GL_FRAMEBUFFER_COMPLETE_EXT) { ++ /* this may occur when we're called by glBindFrameBuffer() during ++ * the process of someone setting up renderbuffers, etc. ++ */ ++ /*_mesa_debug(ctx, "DrawBuffer: incomplete user FBO\n");*/ ++ return; ++ } ++ ++ if (fb->Name) ++ ;/* do something depthy/stencily TODO */ ++ ++ ++ /* none */ ++ if (fb->Name == 0) { ++ if (fb->_ColorDrawBufferIndexes[0] == BUFFER_FRONT_LEFT) { ++ rrbColor = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; ++ radeon->front_cliprects = GL_TRUE; ++ } else { ++ rrbColor = (void *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; ++ radeon->front_cliprects = GL_FALSE; ++ } ++ } else { ++ /* user FBO in theory */ ++ struct radeon_renderbuffer *rrb; ++ rrb = (void *)fb->_ColorDrawBuffers[0]; ++ rrbColor = rrb; ++ radeon->constant_cliprect = GL_TRUE; ++ } ++ ++ if (rrbColor == NULL) ++ radeon->vtbl.fallback(ctx, RADEON_FALLBACK_DRAW_BUFFER, GL_TRUE); ++ else ++ radeon->vtbl.fallback(ctx, RADEON_FALLBACK_DRAW_BUFFER, GL_FALSE); ++ ++ ++ ++ if (fb->_DepthBuffer && fb->_DepthBuffer->Wrapped) { ++ rrbDepth = (struct radeon_renderbuffer *)fb->_DepthBuffer->Wrapped; ++ if (rrbDepth && rrbDepth->bo) { ++ radeon->vtbl.fallback(ctx, RADEON_FALLBACK_DEPTH_BUFFER, GL_FALSE); ++ } else { ++ radeon->vtbl.fallback(ctx, RADEON_FALLBACK_DEPTH_BUFFER, GL_TRUE); ++ } ++ } else { ++ radeon->vtbl.fallback(ctx, RADEON_FALLBACK_DEPTH_BUFFER, GL_FALSE); ++ rrbDepth = NULL; ++ } ++ ++ /* TODO stencil things */ ++ if (fb->_StencilBuffer && fb->_StencilBuffer->Wrapped) { ++ rrbStencil = (struct radeon_renderbuffer *)fb->_DepthBuffer->Wrapped; ++ if (rrbStencil && rrbStencil->bo) { ++ radeon->vtbl.fallback(ctx, RADEON_FALLBACK_STENCIL_BUFFER, GL_FALSE); ++ /* need to re-compute stencil hw state */ ++ if (ctx->Driver.Enable != NULL) ++ ctx->Driver.Enable(ctx, GL_STENCIL_TEST, ctx->Stencil.Enabled); ++ else ++ ctx->NewState |= _NEW_STENCIL; ++ if (!rrbDepth) ++ rrbDepth = rrbStencil; ++ } else { ++ radeon->vtbl.fallback(ctx, RADEON_FALLBACK_STENCIL_BUFFER, GL_TRUE); ++ } ++ } else { ++ radeon->vtbl.fallback(ctx, RADEON_FALLBACK_STENCIL_BUFFER, GL_FALSE); ++ if (ctx->Driver.Enable != NULL) ++ ctx->Driver.Enable(ctx, GL_STENCIL_TEST, ctx->Stencil.Enabled); ++ else ++ ctx->NewState |= _NEW_STENCIL; ++ } ++ ++ /* Update culling direction which changes depending on the ++ * orientation of the buffer: ++ */ ++ if (ctx->Driver.FrontFace) ++ ctx->Driver.FrontFace(ctx, ctx->Polygon.FrontFace); ++ else ++ ctx->NewState |= _NEW_POLYGON; ++ ++ /* ++ * Update depth test state ++ */ ++ if (ctx->Driver.Enable) { ++ if (ctx->Depth.Test && fb->Visual.depthBits > 0) { ++ ctx->Driver.Enable(ctx, GL_DEPTH_TEST, GL_TRUE); ++ } else { ++ ctx->Driver.Enable(ctx, GL_DEPTH_TEST, GL_FALSE); ++ } ++ } else { ++ ctx->NewState |= _NEW_DEPTH; ++ } ++ ++ radeon->state.depth.rrb = rrbDepth; ++ ++ radeon->state.color.rrb = rrbColor; ++ ++ /* update viewport since it depends on window size */ ++ if (ctx->Driver.Viewport) { ++ ctx->Driver.Viewport(ctx, ctx->Viewport.X, ctx->Viewport.Y, ++ ctx->Viewport.Width, ctx->Viewport.Height); ++ } else { ++ ctx->NewState |= _NEW_VIEWPORT; ++ } ++ ++ /* Set state we know depends on drawable parameters: ++ */ ++ if (ctx->Driver.Scissor) ++ ctx->Driver.Scissor(ctx, ctx->Scissor.X, ctx->Scissor.Y, ++ ctx->Scissor.Width, ctx->Scissor.Height); ++ radeon->NewGLState |= _NEW_SCISSOR; ++} ++ ++/** ++ * Called via glDrawBuffer. ++ */ ++void radeonDrawBuffer( GLcontext *ctx, GLenum mode ) ++{ ++ radeonContextPtr radeon = RADEON_CONTEXT(ctx); ++ ++ if (RADEON_DEBUG & DEBUG_DRI) ++ fprintf(stderr, "%s %s\n", __FUNCTION__, ++ _mesa_lookup_enum_by_nr( mode )); ++ ++ radeon_firevertices(radeon); /* don't pipeline cliprect changes */ ++ ++ radeon_draw_buffer(ctx, ctx->DrawBuffer); ++} ++ ++void radeonReadBuffer( GLcontext *ctx, GLenum mode ) ++{ ++ /* nothing, until we implement h/w glRead/CopyPixels or CopyTexImage */ ++ if (ctx->ReadBuffer == ctx->DrawBuffer) { ++ /* This will update FBO completeness status. ++ * A framebuffer will be incomplete if the GL_READ_BUFFER setting ++ * refers to a missing renderbuffer. Calling glReadBuffer can set ++ * that straight and can make the drawing buffer complete. ++ */ ++ radeon_draw_buffer(ctx, ctx->DrawBuffer); ++ } ++} ++ ++ ++/* Turn on/off page flipping according to the flags in the sarea: ++ */ ++void radeonUpdatePageFlipping(radeonContextPtr radeon) ++{ ++ struct radeon_framebuffer *rfb = radeon->dri.drawable->driverPrivate; ++ ++ rfb->pf_active = radeon->sarea->pfState; ++ rfb->pf_current_page = radeon->sarea->pfCurrentPage; ++ rfb->pf_num_pages = 2; ++ radeon_flip_renderbuffers(rfb); ++ radeon_draw_buffer(radeon->glCtx, radeon->glCtx->DrawBuffer); ++} ++ ++void radeon_window_moved(radeonContextPtr radeon) ++{ ++ GLcontext *ctx = radeon->glCtx; ++ __DRIdrawablePrivate *dPriv = radeon->dri.drawable; ++ struct radeon_framebuffer *rfb = dPriv->driverPrivate; ++ ++ if (!radeon->radeonScreen->driScreen->dri2.enabled) { ++ radeonUpdatePageFlipping(radeon); ++ } ++ radeonSetCliprects(radeon); ++} ++ ++void radeon_viewport(GLcontext *ctx, GLint x, GLint y, GLsizei width, GLsizei height) ++{ ++ radeonContextPtr radeon = RADEON_CONTEXT(ctx); ++ __DRIcontext *driContext = radeon->dri.context; ++ void (*old_viewport)(GLcontext *ctx, GLint x, GLint y, ++ GLsizei w, GLsizei h); ++ ++ if (!driContext->driScreenPriv->dri2.enabled) ++ return; ++ ++ radeon_update_renderbuffers(driContext, driContext->driDrawablePriv); ++ if (driContext->driDrawablePriv != driContext->driReadablePriv) ++ radeon_update_renderbuffers(driContext, driContext->driReadablePriv); ++ ++ old_viewport = ctx->Driver.Viewport; ++ ctx->Driver.Viewport = NULL; ++ radeon->dri.drawable = driContext->driDrawablePriv; ++ radeon_window_moved(radeon); ++ radeon_draw_buffer(ctx, radeon->glCtx->DrawBuffer); ++ ctx->Driver.Viewport = old_viewport; ++ ++ ++} +static void radeon_print_state_atom(radeonContextPtr radeon, struct radeon_state_atom *state ) +{ + int i; @@ -21657,10 +22147,10 @@ index 0000000..f7c0d7d + diff --git a/src/mesa/drivers/dri/radeon/radeon_common.h b/src/mesa/drivers/dri/radeon/radeon_common.h new file mode 100644 -index 0000000..ead0f55 +index 0000000..95b7181 --- /dev/null +++ b/src/mesa/drivers/dri/radeon/radeon_common.h -@@ -0,0 +1,55 @@ +@@ -0,0 +1,60 @@ +#ifndef COMMON_MISC_H +#define COMMON_MISC_H + @@ -21677,7 +22167,6 @@ index 0000000..ead0f55 +extern uint32_t radeonGetAge(radeonContextPtr radeon); +void radeonCopyBuffer( __DRIdrawablePrivate *dPriv, + const drm_clip_rect_t *rect); -+void radeonPageFlip( __DRIdrawablePrivate *dPriv ); +void radeonSwapBuffers(__DRIdrawablePrivate * dPriv); +void radeonCopySubBuffer(__DRIdrawablePrivate * dPriv, + int x, int y, int w, int h ); @@ -21688,6 +22177,12 @@ index 0000000..ead0f55 +void radeonFinish(GLcontext * ctx); +void radeonEmitState(radeonContextPtr radeon); + ++void radeon_window_moved(radeonContextPtr radeon); ++void radeon_draw_buffer(GLcontext *ctx, struct gl_framebuffer *fb); ++void radeonDrawBuffer( GLcontext *ctx, GLenum mode ); ++void radeonReadBuffer( GLcontext *ctx, GLenum mode ); ++void radeon_viewport(GLcontext *ctx, GLint x, GLint y, GLsizei width, GLsizei height); ++ +static inline struct radeon_renderbuffer *radeon_get_depthbuffer(radeonContextPtr rmesa) +{ + struct radeon_renderbuffer *rrb; @@ -21701,11 +22196,11 @@ index 0000000..ead0f55 +static inline struct radeon_renderbuffer *radeon_get_colorbuffer(radeonContextPtr rmesa) +{ + struct radeon_renderbuffer *rrb; -+ GLframebuffer *fb = rmesa->dri.drawable->driverPrivate; ++ struct radeon_framebuffer *rfb = rmesa->dri.drawable->driverPrivate; + + rrb = rmesa->state.color.rrb; + if (rmesa->radeonScreen->driScreen->dri2.enabled) { -+ rrb = (struct radeon_renderbuffer *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; ++ rrb = (struct radeon_renderbuffer *)rfb->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer; + } + if (!rrb) + return NULL; @@ -21718,10 +22213,10 @@ index 0000000..ead0f55 +#endif diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.c b/src/mesa/drivers/dri/radeon/radeon_common_context.c new file mode 100644 -index 0000000..1b8a05d +index 0000000..b63aba2 --- /dev/null +++ b/src/mesa/drivers/dri/radeon/radeon_common_context.c -@@ -0,0 +1,589 @@ +@@ -0,0 +1,591 @@ +/************************************************************************** + +Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and @@ -21759,7 +22254,6 @@ index 0000000..1b8a05d +#include "radeon_common.h" +#include "xmlpool.h" /* for symbolic values of enum-type options */ +#include "utils.h" -+#include "drirenderbuffer.h" +#include "vblank.h" +#include "main/state.h" + @@ -21889,8 +22383,6 @@ index 0000000..1b8a05d + radeon->do_usleeps ? "usleeps" : "busy waits", + fthrottle_mode, radeon->radeonScreen->irq); + -+ (*sPriv->systemTime->getUST) (&radeon->swap_ust); -+ + return GL_TRUE; +} + @@ -21904,39 +22396,39 @@ index 0000000..1b8a05d + FILE *track; +#endif + struct radeon_renderbuffer *rb; -+ GLframebuffer *fb; ++ struct radeon_framebuffer *rfb; + + /* free the Mesa context */ + _mesa_destroy_context(radeon->glCtx); + -+ fb = (void*)radeon->dri.drawable->driverPrivate; -+ rb = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; ++ rfb = (void*)radeon->dri.drawable->driverPrivate; ++ rb = (void *)rfb->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer; + if (rb && rb->bo) { + radeon_bo_unref(rb->bo); + rb->bo = NULL; + } -+ rb = (void *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; ++ rb = (void *)rfb->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer; + if (rb && rb->bo) { + radeon_bo_unref(rb->bo); + rb->bo = NULL; + } -+ rb = (void *)fb->Attachment[BUFFER_DEPTH].Renderbuffer; ++ rb = (void *)rfb->base.Attachment[BUFFER_DEPTH].Renderbuffer; + if (rb && rb->bo) { + radeon_bo_unref(rb->bo); + rb->bo = NULL; + } -+ fb = (void*)radeon->dri.readable->driverPrivate; -+ rb = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; ++ rfb = (void*)radeon->dri.readable->driverPrivate; ++ rb = (void *)rfb->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer; + if (rb && rb->bo) { + radeon_bo_unref(rb->bo); + rb->bo = NULL; + } -+ rb = (void *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; ++ rb = (void *)rfb->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer; + if (rb && rb->bo) { + radeon_bo_unref(rb->bo); + rb->bo = NULL; + } -+ rb = (void *)fb->Attachment[BUFFER_DEPTH].Renderbuffer; ++ rb = (void *)rfb->base.Attachment[BUFFER_DEPTH].Renderbuffer; + if (rb && rb->bo) { + radeon_bo_unref(rb->bo); + rb->bo = NULL; @@ -21984,12 +22476,12 @@ index 0000000..1b8a05d + +static void +radeon_make_kernel_renderbuffer_current(radeonContextPtr radeon, -+ GLframebuffer *draw) ++ struct radeon_framebuffer *draw) +{ + /* if radeon->fake */ + struct radeon_renderbuffer *rb; + -+ if ((rb = (void *)draw->Attachment[BUFFER_FRONT_LEFT].Renderbuffer)) { ++ if ((rb = (void *)draw->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer)) { + if (!rb->bo) { + rb->bo = radeon_bo_open(radeon->radeonScreen->bom, + radeon->radeonScreen->frontOffset, @@ -22001,7 +22493,7 @@ index 0000000..1b8a05d + rb->cpp = radeon->radeonScreen->cpp; + rb->pitch = radeon->radeonScreen->frontPitch * rb->cpp; + } -+ if ((rb = (void *)draw->Attachment[BUFFER_BACK_LEFT].Renderbuffer)) { ++ if ((rb = (void *)draw->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer)) { + if (!rb->bo) { + rb->bo = radeon_bo_open(radeon->radeonScreen->bom, + radeon->radeonScreen->backOffset, @@ -22013,7 +22505,7 @@ index 0000000..1b8a05d + rb->cpp = radeon->radeonScreen->cpp; + rb->pitch = radeon->radeonScreen->backPitch * rb->cpp; + } -+ if ((rb = (void *)draw->Attachment[BUFFER_DEPTH].Renderbuffer)) { ++ if ((rb = (void *)draw->base.Attachment[BUFFER_DEPTH].Renderbuffer)) { + if (!rb->bo) { + rb->bo = radeon_bo_open(radeon->radeonScreen->bom, + radeon->radeonScreen->depthOffset, @@ -22025,7 +22517,7 @@ index 0000000..1b8a05d + rb->cpp = radeon->radeonScreen->cpp; + rb->pitch = radeon->radeonScreen->depthPitch * rb->cpp; + } -+ if ((rb = (void *)draw->Attachment[BUFFER_STENCIL].Renderbuffer)) { ++ if ((rb = (void *)draw->base.Attachment[BUFFER_STENCIL].Renderbuffer)) { + if (!rb->bo) { + rb->bo = radeon_bo_open(radeon->radeonScreen->bom, + radeon->radeonScreen->depthOffset, @@ -22041,7 +22533,7 @@ index 0000000..1b8a05d + +static void +radeon_make_renderbuffer_current(radeonContextPtr radeon, -+ GLframebuffer *draw) ++ struct radeon_framebuffer *draw) +{ + int size = 4096*4096*4; + /* if radeon->fake */ @@ -22053,7 +22545,7 @@ index 0000000..1b8a05d + } + + -+ if ((rb = (void *)draw->Attachment[BUFFER_FRONT_LEFT].Renderbuffer)) { ++ if ((rb = (void *)draw->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer)) { + if (!rb->bo) { + rb->bo = radeon_bo_open(radeon->radeonScreen->bom, + radeon->radeonScreen->frontOffset + @@ -22066,7 +22558,7 @@ index 0000000..1b8a05d + rb->cpp = radeon->radeonScreen->cpp; + rb->pitch = radeon->radeonScreen->frontPitch * rb->cpp; + } -+ if ((rb = (void *)draw->Attachment[BUFFER_BACK_LEFT].Renderbuffer)) { ++ if ((rb = (void *)draw->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer)) { + if (!rb->bo) { + rb->bo = radeon_bo_open(radeon->radeonScreen->bom, + radeon->radeonScreen->backOffset + @@ -22079,7 +22571,7 @@ index 0000000..1b8a05d + rb->cpp = radeon->radeonScreen->cpp; + rb->pitch = radeon->radeonScreen->backPitch * rb->cpp; + } -+ if ((rb = (void *)draw->Attachment[BUFFER_DEPTH].Renderbuffer)) { ++ if ((rb = (void *)draw->base.Attachment[BUFFER_DEPTH].Renderbuffer)) { + if (!rb->bo) { + rb->bo = radeon_bo_open(radeon->radeonScreen->bom, + radeon->radeonScreen->depthOffset + @@ -22092,7 +22584,7 @@ index 0000000..1b8a05d + rb->cpp = radeon->radeonScreen->cpp; + rb->pitch = radeon->radeonScreen->depthPitch * rb->cpp; + } -+ if ((rb = (void *)draw->Attachment[BUFFER_STENCIL].Renderbuffer)) { ++ if ((rb = (void *)draw->base.Attachment[BUFFER_STENCIL].Renderbuffer)) { + if (!rb->bo) { + rb->bo = radeon_bo_open(radeon->radeonScreen->bom, + radeon->radeonScreen->depthOffset + @@ -22116,7 +22608,7 @@ index 0000000..1b8a05d + __DRIscreen *screen; + struct radeon_renderbuffer *rb; + int i, count; -+ GLframebuffer *draw; ++ struct radeon_framebuffer *draw; + radeonContextPtr radeon; + + if (RADEON_DEBUG & DEBUG_DRI) @@ -22126,13 +22618,13 @@ index 0000000..1b8a05d + screen = context->driScreenPriv; + radeon = (radeonContextPtr) context->driverPrivate; + i = 0; -+ if ((rb = (void *)draw->Attachment[BUFFER_FRONT_LEFT].Renderbuffer)) { ++ if ((rb = (void *)draw->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer)) { + attachments[i++] = __DRI_BUFFER_FRONT_LEFT; + } -+ if ((rb = (void *)draw->Attachment[BUFFER_BACK_LEFT].Renderbuffer)) { ++ if ((rb = (void *)draw->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer)) { + attachments[i++] = __DRI_BUFFER_BACK_LEFT; + } -+ if ((rb = (void *)draw->Attachment[BUFFER_DEPTH].Renderbuffer)) { ++ if ((rb = (void *)draw->base.Attachment[BUFFER_DEPTH].Renderbuffer)) { + attachments[i++] = __DRI_BUFFER_DEPTH; + } + @@ -22163,7 +22655,7 @@ index 0000000..1b8a05d + for (i = 0; i < count; i++) { + switch (buffers[i].attachment) { + case __DRI_BUFFER_FRONT_LEFT: -+ rb = (void *)draw->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; ++ rb = (void *)draw->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer; + if (rb->bo) { + radeon_bo_unref(rb->bo); + rb->bo = NULL; @@ -22185,7 +22677,7 @@ index 0000000..1b8a05d + } + break; + case __DRI_BUFFER_BACK_LEFT: -+ rb = (void *)draw->Attachment[BUFFER_BACK_LEFT].Renderbuffer; ++ rb = (void *)draw->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer; + if (rb->bo) { + radeon_bo_unref(rb->bo); + rb->bo = NULL; @@ -22203,7 +22695,7 @@ index 0000000..1b8a05d + buffers[i].flags); + break; + case __DRI_BUFFER_DEPTH: -+ rb = (void *)draw->Attachment[BUFFER_DEPTH].Renderbuffer; ++ rb = (void *)draw->base.Attachment[BUFFER_DEPTH].Renderbuffer; + if (rb->bo) { + radeon_bo_unref(rb->bo); + rb->bo = NULL; @@ -22242,7 +22734,8 @@ index 0000000..1b8a05d + __DRIdrawablePrivate * driReadPriv) +{ + radeonContextPtr radeon; -+ GLframebuffer *dfb, *rfb; ++ struct radeon_framebuffer *drfb; ++ struct gl_framebuffer *readfb; + + if (!driContextPriv) { + if (RADEON_DEBUG & DEBUG_DRI) @@ -22250,62 +22743,66 @@ index 0000000..1b8a05d + _mesa_make_current(NULL, NULL, NULL); + return GL_TRUE; + } ++ + radeon = (radeonContextPtr) driContextPriv->driverPrivate; -+ dfb = driDrawPriv->driverPrivate; -+ rfb = driReadPriv->driverPrivate; ++ drfb = driDrawPriv->driverPrivate; ++ readfb = driReadPriv->driverPrivate; + + if (driContextPriv->driScreenPriv->dri2.enabled) { + radeon_update_renderbuffers(driContextPriv, driDrawPriv); + if (driDrawPriv != driReadPriv) + radeon_update_renderbuffers(driContextPriv, driReadPriv); + radeon->state.color.rrb = -+ (void *)dfb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; ++ (void *)drfb->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer; + radeon->state.depth.rrb = -+ (void *)dfb->Attachment[BUFFER_DEPTH].Renderbuffer; ++ (void *)drfb->base.Attachment[BUFFER_DEPTH].Renderbuffer; + } else { -+ radeon_make_renderbuffer_current(radeon, dfb); ++ radeon_make_renderbuffer_current(radeon, drfb); + } + + + if (RADEON_DEBUG & DEBUG_DRI) -+ fprintf(stderr, "%s ctx %p dfb %p rfb %p\n", __FUNCTION__, radeon->glCtx, dfb, rfb); ++ fprintf(stderr, "%s ctx %p dfb %p rfb %p\n", __FUNCTION__, radeon->glCtx, drfb, readfb); ++ ++ if (radeon->dri.readable != driReadPriv) ++ radeon->dri.readable = driReadPriv; + + driUpdateFramebufferSize(radeon->glCtx, driDrawPriv); + if (driReadPriv != driDrawPriv) + driUpdateFramebufferSize(radeon->glCtx, driReadPriv); + -+ -+ -+ _mesa_make_current(radeon->glCtx, dfb, rfb); -+ -+ if (radeon->dri.drawable != driDrawPriv) { -+ if (driDrawPriv->swap_interval == (unsigned)-1) { -+ driDrawPriv->vblFlags = -+ (radeon->radeonScreen->irq != 0) -+ ? driGetDefaultVBlankFlags(&radeon-> -+ optionCache) -+ : VBLANK_FLAG_NO_IRQ; -+ -+ driDrawableInitVBlank(driDrawPriv); -+ } -+ } -+ -+ radeon->dri.readable = driReadPriv; -+ -+ if (radeon->dri.drawable != driDrawPriv || -+ radeon->lastStamp != driDrawPriv->lastStamp) { -+ radeon->dri.drawable = driDrawPriv; -+ -+ radeonSetCliprects(radeon); -+ radeon->vtbl.update_viewport_offset(radeon->glCtx); -+ } ++ _mesa_make_current(radeon->glCtx, &drfb->base, readfb); + + _mesa_update_state(radeon->glCtx); + -+ if (!driContextPriv->driScreenPriv->dri2.enabled) { -+ radeonUpdatePageFlipping(radeon); ++ if (radeon->glCtx->DrawBuffer == &drfb->base) { ++ ++ if (radeon->dri.drawable != driDrawPriv) { ++ if (driDrawPriv->swap_interval == (unsigned)-1) { ++ int i; ++ driDrawPriv->vblFlags = ++ (radeon->radeonScreen->irq != 0) ++ ? driGetDefaultVBlankFlags(&radeon-> ++ optionCache) ++ : VBLANK_FLAG_NO_IRQ; ++ ++ driDrawableInitVBlank(driDrawPriv); ++ drfb->vbl_waited = driDrawPriv->vblSeq; ++ ++ for (i = 0; i < 2; i++) { ++ if (drfb->color_rb[i]) ++ drfb->color_rb[i]->vbl_pending = driDrawPriv->vblSeq; ++ } ++ ++ } ++ radeon->dri.drawable = driDrawPriv; ++ ++ radeon_window_moved(radeon); ++ } ++ radeon_draw_buffer(radeon->glCtx, &drfb->base); + } + ++ + if (RADEON_DEBUG & DEBUG_DRI) + fprintf(stderr, "End %s\n", __FUNCTION__); + return GL_TRUE; @@ -22313,10 +22810,10 @@ index 0000000..1b8a05d + diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.h b/src/mesa/drivers/dri/radeon/radeon_common_context.h new file mode 100644 -index 0000000..a200e90 +index 0000000..4aeb50f --- /dev/null +++ b/src/mesa/drivers/dri/radeon/radeon_common_context.h -@@ -0,0 +1,508 @@ +@@ -0,0 +1,529 @@ + +#ifndef COMMON_CONTEXT_H +#define COMMON_CONTEXT_H @@ -22358,6 +22855,8 @@ index 0000000..a200e90 +#define RADEON_FALLBACK_BLEND_FUNC 0x0020 +#define RADEON_FALLBACK_DISABLE 0x0040 +#define RADEON_FALLBACK_BORDER_MODE 0x0080 ++#define RADEON_FALLBACK_DEPTH_BUFFER 0x0100 ++#define RADEON_FALLBACK_STENCIL_BUFFER 0x0200 + +#define R200_FALLBACK_TEXTURE 0x01 +#define R200_FALLBACK_DRAW_BUFFER 0x02 @@ -22400,9 +22899,34 @@ index 0000000..a200e90 + /* boo Xorg 6.8.2 compat */ + int has_surface; + ++ GLuint pf_pending; /**< sequence number of pending flip */ ++ GLuint vbl_pending; /**< vblank sequence number of pending flip */ + __DRIdrawablePrivate *dPriv; +}; + ++struct radeon_framebuffer ++{ ++ struct gl_framebuffer base; ++ ++ struct radeon_renderbuffer *color_rb[2]; ++ ++ GLuint vbl_waited; ++ ++ /* buffer swap */ ++ int64_t swap_ust; ++ int64_t swap_missed_ust; ++ ++ GLuint swap_count; ++ GLuint swap_missed_count; ++ ++ /* Drawable page flipping state */ ++ GLboolean pf_active; ++ GLint pf_current_page; ++ GLint pf_num_pages; ++ ++}; ++ ++ +struct radeon_colorbuffer_state { + GLuint clear; + int roundEnable; @@ -22706,9 +23230,6 @@ index 0000000..a200e90 + GLuint NewGLState; + DECLARE_RENDERINPUTS(tnl_index_bitset); /* index of bits for last tnl_install_attrs */ + -+ /* Page flipping */ -+ GLuint doPageFlip; -+ + /* Drawable, cliprect and scissor information */ + GLuint numClipRects; /* Cliprects for the draw buffer */ + drm_clip_rect_t *pClipRects; @@ -22725,13 +23246,6 @@ index 0000000..a200e90 + GLuint irqsEmitted; + drm_radeon_irq_wait_t iw; + -+ /* buffer swap */ -+ int64_t swap_ust; -+ int64_t swap_missed_ust; -+ -+ GLuint swap_count; -+ GLuint swap_missed_count; -+ + /* Derived state - for r300 only */ + struct radeon_state state; + @@ -22741,15 +23255,19 @@ index 0000000..a200e90 + driOptionCache optionCache; + + struct radeon_cmdbuf cmdbuf; ++ ++ drm_clip_rect_t fboRect; ++ GLboolean constant_cliprect; /* use for FBO or DRI2 rendering */ ++ GLboolean front_cliprects; + + struct { + void (*get_lock)(radeonContextPtr radeon); + void (*update_viewport_offset)(GLcontext *ctx); -+ void (*update_draw_buffer)(GLcontext *ctx); + void (*emit_cs_header)(struct radeon_cs *cs, radeonContextPtr rmesa); + void (*swtcl_flush)(GLcontext *ctx, uint32_t offset); + void (*pre_emit_atoms)(radeonContextPtr rmesa); + void (*pre_emit_state)(radeonContextPtr rmesa); ++ void (*fallback)(GLcontext *ctx, GLuint bit, GLboolean mode); + } vtbl; +}; + @@ -23133,7 +23651,7 @@ index 46b490d..0000000 -} - diff --git a/src/mesa/drivers/dri/radeon/radeon_context.c b/src/mesa/drivers/dri/radeon/radeon_context.c -index 1e992c0..e4202c7 100644 +index 1e992c0..47ebe41 100644 --- a/src/mesa/drivers/dri/radeon/radeon_context.c +++ b/src/mesa/drivers/dri/radeon/radeon_context.c @@ -53,6 +53,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. @@ -23270,10 +23788,10 @@ index 1e992c0..e4202c7 100644 +{ + radeon->vtbl.get_lock = r100_get_lock; + radeon->vtbl.update_viewport_offset = radeonUpdateViewportOffset; -+ radeon->vtbl.update_draw_buffer = radeonUpdateDrawBuffer; + radeon->vtbl.emit_cs_header = r100_vtbl_emit_cs_header; + radeon->vtbl.swtcl_flush = r100_swtcl_flush; + radeon->vtbl.pre_emit_state = r100_vtbl_pre_emit_state; ++ radeon->vtbl.fallback = radeonFallback; +} /* Create the device specific context. @@ -23435,7 +23953,7 @@ index 1e992c0..e4202c7 100644 /* Initialize the software rasterizer and helper modules. */ _swrast_CreateContext( ctx ); -@@ -392,38 +338,38 @@ radeonCreateContext( const __GLcontextModes *glVisual, +@@ -392,38 +338,36 @@ radeonCreateContext( const __GLcontextModes *glVisual, } driInitExtensions( ctx, card_extensions, GL_TRUE ); @@ -23479,14 +23997,13 @@ index 1e992c0..e4202c7 100644 + fthrottle_mode == DRI_CONF_FTHROTTLE_IRQS); - rmesa->do_usleeps = (fthrottle_mode == DRI_CONF_FTHROTTLE_USLEEPS); -+ rmesa->radeon.do_usleeps = (fthrottle_mode == DRI_CONF_FTHROTTLE_USLEEPS); - +- - (*sPriv->systemTime->getUST)( & rmesa->swap_ust ); -+ (*sPriv->systemTime->getUST)( & rmesa->radeon.swap_ust ); ++ rmesa->radeon.do_usleeps = (fthrottle_mode == DRI_CONF_FTHROTTLE_USLEEPS); #if DO_DEBUG -@@ -431,20 +377,20 @@ radeonCreateContext( const __GLcontextModes *glVisual, +@@ -431,20 +375,20 @@ radeonCreateContext( const __GLcontextModes *glVisual, debug_control ); #endif @@ -23514,7 +24031,7 @@ index 1e992c0..e4202c7 100644 /* _tnl_need_dlist_norm_lengths( ctx, GL_FALSE ); */ } return GL_TRUE; -@@ -458,179 +404,41 @@ radeonCreateContext( const __GLcontextModes *glVisual, +@@ -458,179 +402,41 @@ radeonCreateContext( const __GLcontextModes *glVisual, void radeonDestroyContext( __DRIcontextPrivate *driContextPriv ) { GET_CURRENT_CONTEXT(ctx); @@ -23711,7 +24228,7 @@ index 1e992c0..e4202c7 100644 - return GL_TRUE; -} diff --git a/src/mesa/drivers/dri/radeon/radeon_context.h b/src/mesa/drivers/dri/radeon/radeon_context.h -index 53df766..2efabd1 100644 +index 53df766..2015e96 100644 --- a/src/mesa/drivers/dri/radeon/radeon_context.h +++ b/src/mesa/drivers/dri/radeon/radeon_context.h @@ -48,91 +48,23 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. @@ -23776,12 +24293,12 @@ index 53df766..2efabd1 100644 +#include "radeon_common.h" -typedef void (*radeon_point_func) (radeonContextPtr, radeonVertex *); -- + -struct radeon_colorbuffer_state { - GLuint clear; - int roundEnable; -}; - +- -struct radeon_depthbuffer_state { - GLuint clear; - GLfloat scale; @@ -24142,10 +24659,24 @@ index 53df766..2efabd1 100644 GLboolean using_hyperz; GLboolean texmicrotile; -@@ -703,23 +434,11 @@ struct radeon_context { +@@ -703,23 +434,26 @@ struct radeon_context { GLuint c_textureSwaps; GLuint c_textureBytes; GLuint c_vertexBuffers; ++ ++ struct { ++ struct gl_fragment_program *bitmap_fp; ++ struct gl_vertex_program *passthrough_vp; ++ ++ struct gl_fragment_program *saved_fp; ++ GLboolean saved_fp_enable; ++ struct gl_vertex_program *saved_vp; ++ GLboolean saved_vp_enable; ++ ++ GLint saved_vp_x, saved_vp_y; ++ GLsizei saved_vp_width, saved_vp_height; ++ GLenum saved_matrix_mode; ++ } meta; + }; @@ -24164,12 +24695,13 @@ index 53df766..2efabd1 100644 - return 0; - } -} ++ +#define R100_CONTEXT(ctx) ((r100ContextPtr)(ctx->DriverCtx)) + #define RADEON_OLD_PACKETS 1 -@@ -727,37 +446,11 @@ extern void radeonDestroyContext(__DRIcontextPrivate * driContextPriv); +@@ -727,37 +461,11 @@ extern void radeonDestroyContext(__DRIcontextPrivate * driContextPriv); extern GLboolean radeonCreateContext(const __GLcontextModes * glVisual, __DRIcontextPrivate * driContextPriv, void *sharedContextPrivate); @@ -24979,10 +25511,10 @@ index 0000000..e177b4b +#endif diff --git a/src/mesa/drivers/dri/radeon/radeon_dma.c b/src/mesa/drivers/dri/radeon/radeon_dma.c new file mode 100644 -index 0000000..393b121 +index 0000000..01fc20b --- /dev/null +++ b/src/mesa/drivers/dri/radeon/radeon_dma.c -@@ -0,0 +1,323 @@ +@@ -0,0 +1,330 @@ +/************************************************************************** + +Copyright (C) 2004 Nicolai Haehnle. @@ -25260,7 +25792,7 @@ index 0000000..393b121 + + + if (RADEON_DEBUG & DEBUG_IOCTL) -+ fprintf(stderr, "%s\n", __FUNCTION__); ++ fprintf(stderr, "%s %p\n", __FUNCTION__, dma->current); + dma->flush = NULL; + + if (dma->current) { @@ -25285,12 +25817,19 @@ index 0000000..393b121 +{ + GLuint bytes = vsize * nverts; + void *head; -+ ++restart: + if (!rmesa->dma.current || rmesa->dma.current_vertexptr + bytes > rmesa->dma.current->size) { + radeonRefillCurrentDmaRegion(rmesa, bytes); + } + + if (!rmesa->dma.flush) { ++ /* make sure we have enough space to use this in cmdbuf */ ++ rcommonEnsureCmdBufSpace(rmesa, ++ rmesa->hw.max_state_size + (12*sizeof(int)), ++ __FUNCTION__); ++ /* if cmdbuf flushed DMA restart */ ++ if (!rmesa->dma.current) ++ goto restart; + rmesa->glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES; + rmesa->dma.flush = rcommon_flush_last_swtcl_prim; + } @@ -25364,10 +25903,30 @@ index 0000000..cee3744 +void *rcommonAllocDmaLowVerts(radeonContextPtr rmesa, int nverts, int vsize); +#endif diff --git a/src/mesa/drivers/dri/radeon/radeon_ioctl.c b/src/mesa/drivers/dri/radeon/radeon_ioctl.c -index 09acf6b..b5ab923 100644 +index 09acf6b..22584f4 100644 --- a/src/mesa/drivers/dri/radeon/radeon_ioctl.c +++ b/src/mesa/drivers/dri/radeon/radeon_ioctl.c -@@ -43,6 +43,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +@@ -37,12 +37,27 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + #include + #include + ++#include "main/attrib.h" ++#include "main/enable.h" ++#include "main/blend.h" ++#include "main/bufferobj.h" ++#include "main/buffers.h" ++#include "main/depth.h" ++#include "main/shaders.h" ++#include "main/texstate.h" ++#include "main/varray.h" ++#include "glapi/dispatch.h" ++#include "swrast/swrast.h" ++#include "main/stencil.h" ++#include "main/matrix.h" ++ + #include "main/glheader.h" + #include "main/imports.h" + #include "main/simple_list.h" #include "swrast/swrast.h" #include "radeon_context.h" @@ -25375,7 +25934,7 @@ index 09acf6b..b5ab923 100644 #include "radeon_state.h" #include "radeon_ioctl.h" #include "radeon_tcl.h" -@@ -58,75 +59,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +@@ -58,75 +73,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define RADEON_IDLE_RETRY 16 @@ -25451,7 +26010,7 @@ index 09acf6b..b5ab923 100644 /* ============================================================= * Kernel command buffer handling */ -@@ -134,893 +66,340 @@ static void radeonBackUpAndEmitLostStateLocked( radeonContextPtr rmesa ) +@@ -134,965 +80,572 @@ static void radeonBackUpAndEmitLostStateLocked( radeonContextPtr rmesa ) /* The state atoms will be emitted in the order they appear in the atom list, * so this step is important. */ @@ -25702,15 +26261,15 @@ index 09acf6b..b5ab923 100644 - rmesa->store.cmd_used = (rmesa->store.cmd_used + 2) & ~2; - dwords = (rmesa->store.cmd_used - rmesa->store.elts_start) / 4; + nr = rmesa->tcl.elt_used; - - #if RADEON_OLD_PACKETS -- cmd[1] |= (dwords - 3) << 16; ++ ++#if RADEON_OLD_PACKETS + if (rmesa->radeon.radeonScreen->kernel_mm) { + dwords -= 2; + } +#endif -+ -+#if RADEON_OLD_PACKETS + + #if RADEON_OLD_PACKETS +- cmd[1] |= (dwords - 3) << 16; + cmd[1] |= (dwords + 3) << 16; cmd[5] |= nr << RADEON_CP_VC_CNTL_NUM_SHIFT; #else @@ -25830,14 +26389,14 @@ index 09acf6b..b5ab923 100644 - rmesa->dma.flush = radeonFlushElts; + rmesa->tcl.elt_cmd_offset = rmesa->radeon.cmdbuf.cs->cdw; + rmesa->tcl.elt_used = min_nr; - -- rmesa->store.elts_start = ((char *)cmd) - rmesa->store.cmd_buf; ++ + retval = (GLushort *)(rmesa->radeon.cmdbuf.cs->packets + rmesa->tcl.elt_cmd_offset); + + if (RADEON_DEBUG & DEBUG_PRIMS) + fprintf(stderr, "%s: header prim %x \n", + __FUNCTION__, primitive); -+ + +- rmesa->store.elts_start = ((char *)cmd) - rmesa->store.cmd_buf; + assert(!rmesa->radeon.dma.flush); + rmesa->radeon.glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES; + rmesa->radeon.dma.flush = radeonFlushElts; @@ -25928,7 +26487,32 @@ index 09acf6b..b5ab923 100644 - cmd[2].i = (component[i]->aos_start + - offset * component[i]->aos_stride * 4); - cmd += 3; -- } ++ BEGIN_BATCH(sz+2+(nr * 2)); ++ OUT_BATCH_PACKET3(RADEON_CP_PACKET3_3D_LOAD_VBPNTR, sz - 1); ++ OUT_BATCH(nr); ++ ++ if (!rmesa->radeon.radeonScreen->kernel_mm) { ++ for (i = 0; i + 1 < nr; i += 2) { ++ OUT_BATCH((rmesa->tcl.aos[i].components << 0) | ++ (rmesa->tcl.aos[i].stride << 8) | ++ (rmesa->tcl.aos[i + 1].components << 16) | ++ (rmesa->tcl.aos[i + 1].stride << 24)); ++ ++ voffset = rmesa->tcl.aos[i + 0].offset + ++ offset * 4 * rmesa->tcl.aos[i + 0].stride; ++ OUT_BATCH_RELOC(voffset, ++ rmesa->tcl.aos[i].bo, ++ voffset, ++ RADEON_GEM_DOMAIN_GTT, ++ 0, 0); ++ voffset = rmesa->tcl.aos[i + 1].offset + ++ offset * 4 * rmesa->tcl.aos[i + 1].stride; ++ OUT_BATCH_RELOC(voffset, ++ rmesa->tcl.aos[i+1].bo, ++ voffset, ++ RADEON_GEM_DOMAIN_GTT, ++ 0, 0); + } - else { - cmd[0].i = ((component[i]->aos_stride << 8) | - (component[i]->aos_size << 0)); @@ -26046,28 +26630,14 @@ index 09acf6b..b5ab923 100644 - if (ret) { - fprintf(stderr, "drmSanityCommandWrite: %d\n", ret); - goto out; -+ BEGIN_BATCH(sz+2+(nr * 2)); -+ OUT_BATCH_PACKET3(RADEON_CP_PACKET3_3D_LOAD_VBPNTR, sz - 1); -+ OUT_BATCH(nr); -+ -+ if (!rmesa->radeon.radeonScreen->kernel_mm) { -+ for (i = 0; i + 1 < nr; i += 2) { -+ OUT_BATCH((rmesa->tcl.aos[i].components << 0) | -+ (rmesa->tcl.aos[i].stride << 8) | -+ (rmesa->tcl.aos[i + 1].components << 16) | -+ (rmesa->tcl.aos[i + 1].stride << 24)); -+ -+ voffset = rmesa->tcl.aos[i + 0].offset + -+ offset * 4 * rmesa->tcl.aos[i + 0].stride; ++ ++ if (nr & 1) { ++ OUT_BATCH((rmesa->tcl.aos[nr - 1].components << 0) | ++ (rmesa->tcl.aos[nr - 1].stride << 8)); ++ voffset = rmesa->tcl.aos[nr - 1].offset + ++ offset * 4 * rmesa->tcl.aos[nr - 1].stride; + OUT_BATCH_RELOC(voffset, -+ rmesa->tcl.aos[i].bo, -+ voffset, -+ RADEON_GEM_DOMAIN_GTT, -+ 0, 0); -+ voffset = rmesa->tcl.aos[i + 1].offset + -+ offset * 4 * rmesa->tcl.aos[i + 1].stride; -+ OUT_BATCH_RELOC(voffset, -+ rmesa->tcl.aos[i+1].bo, ++ rmesa->tcl.aos[nr - 1].bo, + voffset, + RADEON_GEM_DOMAIN_GTT, + 0, 0); @@ -26081,7 +26651,7 @@ index 09acf6b..b5ab923 100644 - if (rmesa->state.scissor.enabled) { - cmd.nbox = rmesa->state.scissor.numClipRects; - cmd.boxes = rmesa->state.scissor.pClipRects; -- } else { + } else { - cmd.nbox = rmesa->numClipRects; - cmd.boxes = rmesa->pClipRects; - } @@ -26170,35 +26740,12 @@ index 09acf6b..b5ab923 100644 - LOCK_HARDWARE(rmesa); /* no need to validate */ - - ret = drmDMA( fd, &dma ); - +- - if (ret != 0) { - /* Free some up this way? - */ - if (rmesa->dma.nr_released_bufs) { - radeonFlushCmdBufLocked( rmesa, __FUNCTION__ ); -+ if (nr & 1) { -+ OUT_BATCH((rmesa->tcl.aos[nr - 1].components << 0) | -+ (rmesa->tcl.aos[nr - 1].stride << 8)); -+ voffset = rmesa->tcl.aos[nr - 1].offset + -+ offset * 4 * rmesa->tcl.aos[nr - 1].stride; -+ OUT_BATCH_RELOC(voffset, -+ rmesa->tcl.aos[nr - 1].bo, -+ voffset, -+ RADEON_GEM_DOMAIN_GTT, -+ 0, 0); - } -- -- if (RADEON_DEBUG & DEBUG_DMA) -- fprintf(stderr, "Waiting for buffers\n"); -- -- radeonWaitForIdleLocked( rmesa ); -- ret = drmDMA( fd, &dma ); -- -- if ( ret != 0 ) { -- UNLOCK_HARDWARE( rmesa ); -- fprintf( stderr, "Error: Could not get dma buffer... exiting\n" ); -- exit( -1 ); -+ } else { + for (i = 0; i + 1 < nr; i += 2) { + OUT_BATCH((rmesa->tcl.aos[i].components << 0) | + (rmesa->tcl.aos[i].stride << 8) | @@ -26212,8 +26759,49 @@ index 09acf6b..b5ab923 100644 + offset * 4 * rmesa->tcl.aos[i + 1].stride; + OUT_BATCH(voffset); } -- } + +- if (RADEON_DEBUG & DEBUG_DMA) +- fprintf(stderr, "Waiting for buffers\n"); - +- radeonWaitForIdleLocked( rmesa ); +- ret = drmDMA( fd, &dma ); +- +- if ( ret != 0 ) { +- UNLOCK_HARDWARE( rmesa ); +- fprintf( stderr, "Error: Could not get dma buffer... exiting\n" ); +- exit( -1 ); ++ if (nr & 1) { ++ OUT_BATCH((rmesa->tcl.aos[nr - 1].components << 0) | ++ (rmesa->tcl.aos[nr - 1].stride << 8)); ++ voffset = rmesa->tcl.aos[nr - 1].offset + ++ offset * 4 * rmesa->tcl.aos[nr - 1].stride; ++ OUT_BATCH(voffset); ++ } ++ for (i = 0; i + 1 < nr; i += 2) { ++ voffset = rmesa->tcl.aos[i + 0].offset + ++ offset * 4 * rmesa->tcl.aos[i + 0].stride; ++ radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, ++ rmesa->tcl.aos[i+0].bo, ++ RADEON_GEM_DOMAIN_GTT, ++ 0, 0); ++ voffset = rmesa->tcl.aos[i + 1].offset + ++ offset * 4 * rmesa->tcl.aos[i + 1].stride; ++ radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, ++ rmesa->tcl.aos[i+1].bo, ++ RADEON_GEM_DOMAIN_GTT, ++ 0, 0); ++ } ++ if (nr & 1) { ++ voffset = rmesa->tcl.aos[nr - 1].offset + ++ offset * 4 * rmesa->tcl.aos[nr - 1].stride; ++ radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, ++ rmesa->tcl.aos[nr-1].bo, ++ RADEON_GEM_DOMAIN_GTT, ++ 0, 0); + } + } ++ END_BATCH(); + - UNLOCK_HARDWARE(rmesa); - - if (RADEON_DEBUG & DEBUG_DMA) @@ -26230,8 +26818,9 @@ index 09acf6b..b5ab923 100644 - rmesa->dma.current.ptr = 0; - - rmesa->c_vertexBuffers++; --} -- ++#endif + } + -void radeonReleaseDmaRegion( radeonContextPtr rmesa, - struct radeon_dma_region *region, - const char *caller ) @@ -26241,17 +26830,21 @@ index 09acf6b..b5ab923 100644 - - if (!region->buf) - return; -- ++/* ================================================================ ++ * Buffer clear ++ */ ++#define RADEON_MAX_CLEARS 256 + - if (rmesa->dma.flush) - rmesa->dma.flush( rmesa ); -- + - if (--region->buf->refcount == 0) { - drm_radeon_cmd_header_t *cmd; -- + - if (RADEON_DEBUG & (DEBUG_IOCTL|DEBUG_DMA)) - fprintf(stderr, "%s -- DISCARD BUF %d\n", __FUNCTION__, - region->buf->buf->idx); - +- - cmd = (drm_radeon_cmd_header_t *)radeonAllocCmdBuf( rmesa, sizeof(*cmd), - __FUNCTION__ ); - cmd->dma.cmd_type = RADEON_CMD_DMA_DISCARD; @@ -26271,23 +26864,36 @@ index 09acf6b..b5ab923 100644 - struct radeon_dma_region *region, - int bytes, - int alignment ) --{ ++static void ++r100_meta_set_passthrough_transform(r100ContextPtr r100) + { - if (RADEON_DEBUG & DEBUG_IOCTL) - fprintf(stderr, "%s %d\n", __FUNCTION__, bytes); - - if (rmesa->dma.flush) - rmesa->dma.flush( rmesa ); -- ++ GLcontext *ctx = r100->radeon.glCtx; + - if (region->buf) - radeonReleaseDmaRegion( rmesa, region, __FUNCTION__ ); -- ++ r100->meta.saved_vp_x = ctx->Viewport.X; ++ r100->meta.saved_vp_y = ctx->Viewport.Y; ++ r100->meta.saved_vp_width = ctx->Viewport.Width; ++ r100->meta.saved_vp_height = ctx->Viewport.Height; ++ r100->meta.saved_matrix_mode = ctx->Transform.MatrixMode; + - alignment--; - rmesa->dma.current.start = rmesa->dma.current.ptr = - (rmesa->dma.current.ptr + alignment) & ~alignment; -- ++ _mesa_Viewport(0, 0, ctx->DrawBuffer->Width, ctx->DrawBuffer->Height); + - if ( rmesa->dma.current.ptr + bytes > rmesa->dma.current.end ) - radeonRefillCurrentDmaRegion( rmesa ); -- ++ _mesa_MatrixMode(GL_PROJECTION); ++ _mesa_PushMatrix(); ++ _mesa_LoadIdentity(); ++ _mesa_Ortho(0, ctx->DrawBuffer->Width, 0, ctx->DrawBuffer->Height, 1, -1); + - region->start = rmesa->dma.current.start; - region->ptr = rmesa->dma.current.start; - region->end = rmesa->dma.current.start + bytes; @@ -26298,14 +26904,19 @@ index 09acf6b..b5ab923 100644 - rmesa->dma.current.ptr += bytes; /* bug - if alignment > 7 */ - rmesa->dma.current.start = - rmesa->dma.current.ptr = (rmesa->dma.current.ptr + 0x7) & ~0x7; --} -- ++ _mesa_MatrixMode(GL_MODELVIEW); ++ _mesa_PushMatrix(); ++ _mesa_LoadIdentity(); + } + -/* ================================================================ - * SwapBuffers with client-side throttling - */ - -static uint32_t radeonGetLastFrame (radeonContextPtr rmesa) --{ ++static void ++r100_meta_restore_transform(r100ContextPtr r100) + { - drm_radeon_getparam_t gp; - int ret; - uint32_t frame; @@ -26319,10 +26930,15 @@ index 09acf6b..b5ab923 100644 - fprintf( stderr, "%s: drm_radeon_getparam_t: %d\n", __FUNCTION__, ret ); - exit(1); - } -- ++ _mesa_MatrixMode(GL_PROJECTION); ++ _mesa_PopMatrix(); ++ _mesa_MatrixMode(GL_MODELVIEW); ++ _mesa_PopMatrix(); + - return frame; -} -- ++ _mesa_MatrixMode(r100->meta.saved_matrix_mode); + -static void radeonEmitIrqLocked( radeonContextPtr rmesa ) -{ - drm_radeon_irq_emit_t ie; @@ -26335,11 +26951,22 @@ index 09acf6b..b5ab923 100644 - fprintf( stderr, "%s: drm_radeon_irq_emit_t: %d\n", __FUNCTION__, ret ); - exit(1); - } --} -- ++ _mesa_Viewport(r100->meta.saved_vp_x, r100->meta.saved_vp_y, ++ r100->meta.saved_vp_width, r100->meta.saved_vp_height); + } + - -static void radeonWaitIrq( radeonContextPtr rmesa ) --{ ++/** ++ * Perform glClear where mask contains only color, depth, and/or stencil. ++ * ++ * The implementation is based on calling into Mesa to set GL state and ++ * performing normal triangle rendering. The intent of this path is to ++ * have as generic a path as possible, so that any driver could make use of ++ * it. ++ */ ++static void radeon_clear_tris(GLcontext *ctx, GLbitfield mask) + { - int ret; - - do { @@ -26350,7 +26977,56 @@ index 09acf6b..b5ab923 100644 - if ( ret ) { - fprintf( stderr, "%s: drmRadeonIrqWait: %d\n", __FUNCTION__, ret ); - exit(1); -- } ++ r100ContextPtr rmesa = R100_CONTEXT(ctx); ++ GLfloat vertices[4][3]; ++ GLfloat color[4][4]; ++ GLfloat dst_z; ++ struct gl_framebuffer *fb = ctx->DrawBuffer; ++ int i; ++ GLboolean saved_fp_enable = GL_FALSE, saved_vp_enable = GL_FALSE; ++ GLboolean saved_shader_program = 0; ++ unsigned int saved_active_texture; ++ ++ assert((mask & ~(BUFFER_BIT_BACK_LEFT | BUFFER_BIT_FRONT_LEFT | ++ BUFFER_BIT_DEPTH | BUFFER_BIT_STENCIL)) == 0); ++ ++ _mesa_PushAttrib(GL_COLOR_BUFFER_BIT | ++ GL_CURRENT_BIT | ++ GL_DEPTH_BUFFER_BIT | ++ GL_ENABLE_BIT | ++ GL_STENCIL_BUFFER_BIT | ++ GL_TRANSFORM_BIT | ++ GL_CURRENT_BIT); ++ _mesa_PushClientAttrib(GL_CLIENT_VERTEX_ARRAY_BIT); ++ saved_active_texture = ctx->Texture.CurrentUnit; ++ ++ /* Disable existing GL state we don't want to apply to a clear. */ ++ _mesa_Disable(GL_ALPHA_TEST); ++ _mesa_Disable(GL_BLEND); ++ _mesa_Disable(GL_CULL_FACE); ++ _mesa_Disable(GL_FOG); ++ _mesa_Disable(GL_POLYGON_SMOOTH); ++ _mesa_Disable(GL_POLYGON_STIPPLE); ++ _mesa_Disable(GL_POLYGON_OFFSET_FILL); ++ _mesa_Disable(GL_LIGHTING); ++ _mesa_Disable(GL_CLIP_PLANE0); ++ _mesa_Disable(GL_CLIP_PLANE1); ++ _mesa_Disable(GL_CLIP_PLANE2); ++ _mesa_Disable(GL_CLIP_PLANE3); ++ _mesa_Disable(GL_CLIP_PLANE4); ++ _mesa_Disable(GL_CLIP_PLANE5); ++ if (ctx->Extensions.ARB_fragment_program && ctx->FragmentProgram.Enabled) { ++ saved_fp_enable = GL_TRUE; ++ _mesa_Disable(GL_FRAGMENT_PROGRAM_ARB); ++ } ++ if (ctx->Extensions.ARB_vertex_program && ctx->VertexProgram.Enabled) { ++ saved_vp_enable = GL_TRUE; ++ _mesa_Disable(GL_VERTEX_PROGRAM_ARB); ++ } ++ if (ctx->Extensions.ARB_shader_objects && ctx->Shader.CurrentProgram) { ++ saved_shader_program = ctx->Shader.CurrentProgram->Name; ++ _mesa_UseProgramObjectARB(0); + } -} - - @@ -26368,20 +27044,30 @@ index 09acf6b..b5ab923 100644 - UNLOCK_HARDWARE( rmesa ); - radeonWaitIrq( rmesa ); - LOCK_HARDWARE( rmesa ); -- } ++ ++ if (ctx->Texture._EnabledUnits != 0) { ++ int i; ++ ++ for (i = 0; i < ctx->Const.MaxTextureUnits; i++) { ++ _mesa_ActiveTextureARB(GL_TEXTURE0 + i); ++ _mesa_Disable(GL_TEXTURE_1D); ++ _mesa_Disable(GL_TEXTURE_2D); ++ _mesa_Disable(GL_TEXTURE_3D); ++ if (ctx->Extensions.ARB_texture_cube_map) ++ _mesa_Disable(GL_TEXTURE_CUBE_MAP_ARB); ++ if (ctx->Extensions.NV_texture_rectangle) ++ _mesa_Disable(GL_TEXTURE_RECTANGLE_NV); ++ if (ctx->Extensions.MESA_texture_array) { ++ _mesa_Disable(GL_TEXTURE_1D_ARRAY_EXT); ++ _mesa_Disable(GL_TEXTURE_2D_ARRAY_EXT); + } - rmesa->irqsEmitted = 10; - } - - if (rmesa->irqsEmitted) { - radeonEmitIrqLocked( rmesa ); - rmesa->irqsEmitted--; -+ if (nr & 1) { -+ OUT_BATCH((rmesa->tcl.aos[nr - 1].components << 0) | -+ (rmesa->tcl.aos[nr - 1].stride << 8)); -+ voffset = rmesa->tcl.aos[nr - 1].offset + -+ offset * 4 * rmesa->tcl.aos[nr - 1].stride; -+ OUT_BATCH(voffset); - } +- } - } - else { - while (radeonGetLastFrame (rmesa) < sarea->last_frame) { @@ -26389,8 +27075,8 @@ index 09acf6b..b5ab923 100644 - if (rmesa->do_usleeps) - DO_USLEEP( 1 ); - LOCK_HARDWARE( rmesa ); -- } -- } + } + } -} - -/* Copy the back color buffer to the front color buffer. @@ -26412,14 +27098,27 @@ index 09acf6b..b5ab923 100644 - - if ( RADEON_DEBUG & DEBUG_IOCTL ) { - fprintf( stderr, "\n%s( %p )\n\n", __FUNCTION__, (void *) rmesa->glCtx ); -- } -- ++ ++ r100_meta_set_passthrough_transform(rmesa); ++ ++ for (i = 0; i < 4; i++) { ++ color[i][0] = ctx->Color.ClearColor[0]; ++ color[i][1] = ctx->Color.ClearColor[1]; ++ color[i][2] = ctx->Color.ClearColor[2]; ++ color[i][3] = ctx->Color.ClearColor[3]; + } + - RADEON_FIREVERTICES( rmesa ); - LOCK_HARDWARE( rmesa ); - - /* Throttle the frame rate -- only allow one pending swap buffers - * request at a time. -- */ ++ /* convert clear Z from [0,1] to NDC coord in [-1,1] */ ++ dst_z = -1.0 + 2.0 * ctx->Depth.Clear; ++ ++ /* Prepare the vertices, which are the same regardless of which buffer we're ++ * drawing to. + */ - radeonWaitForFrameCompletion( rmesa ); - if (!rect) - { @@ -26454,22 +27153,54 @@ index 09acf6b..b5ab923 100644 - if (b->x1 >= b->x2 || b->y1 >= b->y2) - continue; - } -- ++ vertices[0][0] = fb->_Xmin; ++ vertices[0][1] = fb->_Ymin; ++ vertices[0][2] = dst_z; ++ vertices[1][0] = fb->_Xmax; ++ vertices[1][1] = fb->_Ymin; ++ vertices[1][2] = dst_z; ++ vertices[2][0] = fb->_Xmax; ++ vertices[2][1] = fb->_Ymax; ++ vertices[2][2] = dst_z; ++ vertices[3][0] = fb->_Xmin; ++ vertices[3][1] = fb->_Ymax; ++ vertices[3][2] = dst_z; ++ ++ _mesa_ColorPointer(4, GL_FLOAT, 4 * sizeof(GLfloat), &color); ++ _mesa_VertexPointer(3, GL_FLOAT, 3 * sizeof(GLfloat), &vertices); ++ _mesa_Enable(GL_COLOR_ARRAY); ++ _mesa_Enable(GL_VERTEX_ARRAY); ++ ++ while (mask != 0) { ++ GLuint this_mask = 0; ++ ++ if (mask & BUFFER_BIT_BACK_LEFT) ++ this_mask = BUFFER_BIT_BACK_LEFT; ++ else if (mask & BUFFER_BIT_FRONT_LEFT) ++ this_mask = BUFFER_BIT_FRONT_LEFT; ++ ++ /* Clear depth/stencil in the same pass as color. */ ++ this_mask |= (mask & (BUFFER_BIT_DEPTH | BUFFER_BIT_STENCIL)); ++ ++ /* Select the current color buffer and use the color write mask if ++ * we have one, otherwise don't write any color channels. ++ */ ++ if (this_mask & BUFFER_BIT_FRONT_LEFT) ++ _mesa_DrawBuffer(GL_FRONT_LEFT); ++ else if (this_mask & BUFFER_BIT_BACK_LEFT) ++ _mesa_DrawBuffer(GL_BACK_LEFT); ++ else ++ _mesa_ColorMask(GL_FALSE, GL_FALSE, GL_FALSE, GL_FALSE); + - b++; - n++; -+ for (i = 0; i + 1 < nr; i += 2) { -+ voffset = rmesa->tcl.aos[i + 0].offset + -+ offset * 4 * rmesa->tcl.aos[i + 0].stride; -+ radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, -+ rmesa->tcl.aos[i+0].bo, -+ RADEON_GEM_DOMAIN_GTT, -+ 0, 0); -+ voffset = rmesa->tcl.aos[i + 1].offset + -+ offset * 4 * rmesa->tcl.aos[i + 1].stride; -+ radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, -+ rmesa->tcl.aos[i+1].bo, -+ RADEON_GEM_DOMAIN_GTT, -+ 0, 0); ++ /* Control writing of the depth clear value to depth. */ ++ if (this_mask & BUFFER_BIT_DEPTH) { ++ _mesa_DepthFunc(GL_ALWAYS); ++ _mesa_Enable(GL_DEPTH_TEST); ++ } else { ++ _mesa_Disable(GL_DEPTH_TEST); ++ _mesa_DepthMask(GL_FALSE); } - rmesa->sarea->nbox = n; - @@ -26477,22 +27208,22 @@ index 09acf6b..b5ab923 100644 - continue; - - ret = drmCommandNone( rmesa->dri.fd, DRM_RADEON_SWAP ); -- + - if ( ret ) { - fprintf( stderr, "DRM_RADEON_SWAP_BUFFERS: return = %d\n", ret ); - UNLOCK_HARDWARE( rmesa ); - exit( 1 ); -+ if (nr & 1) { -+ voffset = rmesa->tcl.aos[nr - 1].offset + -+ offset * 4 * rmesa->tcl.aos[nr - 1].stride; -+ radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, -+ rmesa->tcl.aos[nr-1].bo, -+ RADEON_GEM_DOMAIN_GTT, -+ 0, 0); ++ /* Control writing of the stencil clear value to stencil. */ ++ if (this_mask & BUFFER_BIT_STENCIL) { ++ _mesa_Enable(GL_STENCIL_TEST); ++ _mesa_StencilOp(GL_REPLACE, GL_REPLACE, GL_REPLACE); ++ _mesa_StencilFuncSeparate(GL_FRONT, GL_ALWAYS, ctx->Stencil.Clear, ++ ctx->Stencil.WriteMask[0]); ++ } else { ++ _mesa_Disable(GL_STENCIL_TEST); } - } -+ END_BATCH(); - +- } +- - UNLOCK_HARDWARE( rmesa ); - if (!rect) - { @@ -26522,7 +27253,7 @@ index 09acf6b..b5ab923 100644 - - rmesa = (radeonContextPtr) dPriv->driContextPriv->driverPrivate; - psp = dPriv->driScreenPriv; -- + - if ( RADEON_DEBUG & DEBUG_IOCTL ) { - fprintf(stderr, "%s: pfCurrentPage: %d\n", __FUNCTION__, - rmesa->sarea->pfCurrentPage); @@ -26540,7 +27271,8 @@ index 09acf6b..b5ab923 100644 - b[0] = box[0]; - rmesa->sarea->nbox = 1; - } -- ++ CALL_DrawArrays(ctx->Exec, (GL_TRIANGLE_FAN, 0, 4)); + - /* Throttle the frame rate -- only allow a few pending swap buffers - * request at a time. - */ @@ -26550,13 +27282,20 @@ index 09acf6b..b5ab923 100644 - if ( missed_target ) { - rmesa->swap_missed_count++; - (void) (*psp->systemTime->getUST)( & rmesa->swap_missed_ust ); -- } ++ mask &= ~this_mask; + } - LOCK_HARDWARE( rmesa ); -- + - ret = drmCommandNone( rmesa->dri.fd, DRM_RADEON_FLIP ); -- ++ r100_meta_restore_transform(rmesa); + - UNLOCK_HARDWARE( rmesa ); -- ++ _mesa_ActiveTextureARB(GL_TEXTURE0 + saved_active_texture); ++ if (saved_fp_enable) ++ _mesa_Enable(GL_FRAGMENT_PROGRAM_ARB); ++ if (saved_vp_enable) ++ _mesa_Enable(GL_VERTEX_PROGRAM_ARB); + - if ( ret ) { - fprintf( stderr, "DRM_RADEON_FLIP: return = %d\n", ret ); - exit( 1 ); @@ -26564,7 +27303,9 @@ index 09acf6b..b5ab923 100644 - - rmesa->swap_count++; - (void) (*psp->systemTime->getUST)( & rmesa->swap_ust ); -- ++ if (saved_shader_program) ++ _mesa_UseProgramObjectARB(saved_shader_program); + - /* Get ready for drawing next frame. Update the renderbuffers' - * flippedOffset/Pitch fields so we draw into the right place. - */ @@ -26572,68 +27313,96 @@ index 09acf6b..b5ab923 100644 - rmesa->sarea->pfCurrentPage); - - radeonUpdateDrawBuffer(rmesa->glCtx); -+#endif ++ _mesa_PopClientAttrib(); ++ _mesa_PopAttrib(); } -- - /* ================================================================ - * Buffer clear - */ -@@ -1028,9 +407,9 @@ void radeonPageFlip( __DRIdrawablePrivate *dPriv ) ++static void radeonUserClear(GLcontext *ctx, GLuint mask) ++{ ++ radeon_clear_tris(ctx, mask); ++} - static void radeonClear( GLcontext *ctx, GLbitfield mask ) +-/* ================================================================ +- * Buffer clear +- */ +-#define RADEON_MAX_CLEARS 256 +- +-static void radeonClear( GLcontext *ctx, GLbitfield mask ) ++static void radeonKernelClear(GLcontext *ctx, GLuint flags) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); - __DRIdrawablePrivate *dPriv = rmesa->dri.drawable; - drm_radeon_sarea_t *sarea = rmesa->sarea; -+ r100ContextPtr rmesa = R100_CONTEXT(ctx); ++ r100ContextPtr rmesa = R100_CONTEXT(ctx); + __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable; + drm_radeon_sarea_t *sarea = rmesa->radeon.sarea; uint32_t clear; - GLuint flags = 0; - GLuint color_mask = 0; -@@ -1042,8 +421,8 @@ static void radeonClear( GLcontext *ctx, GLbitfield mask ) - } +- GLuint flags = 0; +- GLuint color_mask = 0; + GLint ret, i; + GLint cx, cy, cw, ch; - { +- if ( RADEON_DEBUG & DEBUG_IOCTL ) { +- fprintf( stderr, "radeonClear\n"); +- } +- +- { - LOCK_HARDWARE( rmesa ); - UNLOCK_HARDWARE( rmesa ); -+ LOCK_HARDWARE( &rmesa->radeon ); -+ UNLOCK_HARDWARE( &rmesa->radeon ); - if ( dPriv->numClipRects == 0 ) - return; - } -@@ -1067,7 +446,7 @@ static void radeonClear( GLcontext *ctx, GLbitfield mask ) - mask &= ~BUFFER_BIT_DEPTH; - } - +- if ( dPriv->numClipRects == 0 ) +- return; +- } +- +- radeonFlush( ctx ); +- +- if ( mask & BUFFER_BIT_FRONT_LEFT ) { +- flags |= RADEON_FRONT; +- color_mask = rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK]; +- mask &= ~BUFFER_BIT_FRONT_LEFT; +- } +- +- if ( mask & BUFFER_BIT_BACK_LEFT ) { +- flags |= RADEON_BACK; +- color_mask = rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK]; +- mask &= ~BUFFER_BIT_BACK_LEFT; +- } +- +- if ( mask & BUFFER_BIT_DEPTH ) { +- flags |= RADEON_DEPTH; +- mask &= ~BUFFER_BIT_DEPTH; +- } +- - if ( (mask & BUFFER_BIT_STENCIL) && rmesa->state.stencil.hwBuffer ) { -+ if ( (mask & BUFFER_BIT_STENCIL) && rmesa->radeon.state.stencil.hwBuffer ) { - flags |= RADEON_STENCIL; - mask &= ~BUFFER_BIT_STENCIL; - } -@@ -1083,16 +462,16 @@ static void radeonClear( GLcontext *ctx, GLbitfield mask ) - - if (rmesa->using_hyperz) { - flags |= RADEON_USE_COMP_ZBUF; +- flags |= RADEON_STENCIL; +- mask &= ~BUFFER_BIT_STENCIL; +- } +- +- if ( mask ) { +- if (RADEON_DEBUG & DEBUG_FALLBACKS) +- fprintf(stderr, "%s: swrast clear, mask: %x\n", __FUNCTION__, mask); +- _swrast_Clear( ctx, mask ); +- } +- +- if ( !flags ) +- return; +- +- if (rmesa->using_hyperz) { +- flags |= RADEON_USE_COMP_ZBUF; -/* if (rmesa->radeonScreen->chipset & RADEON_CHIPSET_TCL) -+/* if (rmesa->radeon.radeonScreen->chipset & RADEON_CHIPSET_TCL) - flags |= RADEON_USE_HIERZ; */ +- flags |= RADEON_USE_HIERZ; */ - if (!(rmesa->state.stencil.hwBuffer) || -+ if (!(rmesa->radeon.state.stencil.hwBuffer) || - ((flags & RADEON_DEPTH) && (flags & RADEON_STENCIL) && +- ((flags & RADEON_DEPTH) && (flags & RADEON_STENCIL) && - ((rmesa->state.stencil.clear & RADEON_STENCIL_WRITE_MASK) == RADEON_STENCIL_WRITE_MASK))) { -+ ((rmesa->radeon.state.stencil.clear & RADEON_STENCIL_WRITE_MASK) == RADEON_STENCIL_WRITE_MASK))) { - flags |= RADEON_CLEAR_FASTZ; - } - } - +- flags |= RADEON_CLEAR_FASTZ; +- } +- } +- - LOCK_HARDWARE( rmesa ); + LOCK_HARDWARE( &rmesa->radeon ); /* compute region after locking: */ cx = ctx->DrawBuffer->_Xmin; -@@ -1112,7 +491,7 @@ static void radeonClear( GLcontext *ctx, GLbitfield mask ) +@@ -1112,7 +665,7 @@ static void radeonClear( GLcontext *ctx, GLbitfield mask ) gp.param = RADEON_PARAM_LAST_CLEAR; gp.value = (int *)&clear; @@ -26642,7 +27411,7 @@ index 09acf6b..b5ab923 100644 DRM_RADEON_GETPARAM, &gp, sizeof(gp) ); if ( ret ) { -@@ -1124,20 +503,20 @@ static void radeonClear( GLcontext *ctx, GLbitfield mask ) +@@ -1124,20 +677,20 @@ static void radeonClear( GLcontext *ctx, GLbitfield mask ) break; } @@ -26668,7 +27437,7 @@ index 09acf6b..b5ab923 100644 drm_radeon_clear_t clear; drm_radeon_clear_rect_t depth_boxes[RADEON_NR_SAREA_CLIPRECTS]; GLint n = 0; -@@ -1172,106 +551,40 @@ static void radeonClear( GLcontext *ctx, GLbitfield mask ) +@@ -1172,105 +725,108 @@ static void radeonClear( GLcontext *ctx, GLbitfield mask ) } } @@ -26709,16 +27478,16 @@ index 09acf6b..b5ab923 100644 exit( 1 ); } } - +- - UNLOCK_HARDWARE( rmesa ); - rmesa->hw.all_dirty = GL_TRUE; + UNLOCK_HARDWARE( &rmesa->radeon ); -+ rmesa->radeon.hw.all_dirty = GL_TRUE; } - -void radeonWaitForIdleLocked( radeonContextPtr rmesa ) --{ ++static void radeonClear( GLcontext *ctx, GLbitfield mask ) + { - int fd = rmesa->dri.fd; - int to = 0; - int ret, i = 0; @@ -26737,32 +27506,71 @@ index 09acf6b..b5ab923 100644 - exit( -1 ); - } -} -- -- ++ r100ContextPtr rmesa = R100_CONTEXT(ctx); ++ __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable; ++ GLuint flags = 0; ++ GLuint color_mask = 0; ++ GLuint orig_mask = mask; + ++ if ( RADEON_DEBUG & DEBUG_IOCTL ) { ++ fprintf( stderr, "radeonClear\n"); ++ } + -static void radeonWaitForIdle( radeonContextPtr rmesa ) -{ - LOCK_HARDWARE(rmesa); - radeonWaitForIdleLocked( rmesa ); - UNLOCK_HARDWARE(rmesa); -} -- -- ++ { ++ LOCK_HARDWARE( &rmesa->radeon ); ++ UNLOCK_HARDWARE( &rmesa->radeon ); ++ if ( dPriv->numClipRects == 0 ) ++ return; ++ } ++ ++ radeon_firevertices(&rmesa->radeon); + ++ if ( mask & BUFFER_BIT_FRONT_LEFT ) { ++ flags |= RADEON_FRONT; ++ color_mask = rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK]; ++ mask &= ~BUFFER_BIT_FRONT_LEFT; ++ } + -void radeonFlush( GLcontext *ctx ) -{ - radeonContextPtr rmesa = RADEON_CONTEXT( ctx ); -- ++ if ( mask & BUFFER_BIT_BACK_LEFT ) { ++ flags |= RADEON_BACK; ++ color_mask = rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK]; ++ mask &= ~BUFFER_BIT_BACK_LEFT; ++ } + - if (RADEON_DEBUG & DEBUG_IOCTL) - fprintf(stderr, "%s\n", __FUNCTION__); -- ++ if ( mask & BUFFER_BIT_DEPTH ) { ++ flags |= RADEON_DEPTH; ++ mask &= ~BUFFER_BIT_DEPTH; ++ } + - if (rmesa->dma.flush) - rmesa->dma.flush( rmesa ); -- ++ if ( (mask & BUFFER_BIT_STENCIL) && rmesa->radeon.state.stencil.hwBuffer ) { ++ flags |= RADEON_STENCIL; ++ mask &= ~BUFFER_BIT_STENCIL; ++ } + - radeonEmitState( rmesa ); - - if (rmesa->store.cmd_used) - radeonFlushCmdBuf( rmesa, __FUNCTION__ ); -} -- ++ if ( mask ) { ++ if (RADEON_DEBUG & DEBUG_FALLBACKS) ++ fprintf(stderr, "%s: swrast clear, mask: %x\n", __FUNCTION__, mask); ++ _swrast_Clear( ctx, mask ); ++ } + -/* Make sure all commands have been sent to the hardware and have - * completed processing. - */ @@ -26776,15 +27584,33 @@ index 09acf6b..b5ab923 100644 - radeonEmitIrqLocked( rmesa ); - UNLOCK_HARDWARE( rmesa ); - radeonWaitIrq( rmesa ); -- } ++ if ( !flags ) ++ return; ++ ++ if (rmesa->using_hyperz) { ++ flags |= RADEON_USE_COMP_ZBUF; ++/* if (rmesa->radeon.radeonScreen->chipset & RADEON_CHIPSET_TCL) ++ flags |= RADEON_USE_HIERZ; */ ++ if (!(rmesa->radeon.state.stencil.hwBuffer) || ++ ((flags & RADEON_DEPTH) && (flags & RADEON_STENCIL) && ++ ((rmesa->radeon.state.stencil.clear & RADEON_STENCIL_WRITE_MASK) == RADEON_STENCIL_WRITE_MASK))) { ++ flags |= RADEON_CLEAR_FASTZ; ++ } + } - else - radeonWaitForIdle( rmesa ); -} -- -- + ++ if (rmesa->radeon.radeonScreen->kernel_mm) ++ radeonUserClear(ctx, orig_mask); ++ else { ++ radeonKernelClear(ctx, flags); ++ rmesa->radeon.hw.all_dirty = GL_TRUE; ++ } ++} + void radeonInitIoctlFuncs( GLcontext *ctx ) { - ctx->Driver.Clear = radeonClear; diff --git a/src/mesa/drivers/dri/radeon/radeon_ioctl.h b/src/mesa/drivers/dri/radeon/radeon_ioctl.h index 4e3a44d..18805d4 100644 --- a/src/mesa/drivers/dri/radeon/radeon_ioctl.h @@ -26992,10 +27818,10 @@ index 4e3a44d..18805d4 100644 + #endif /* __RADEON_IOCTL_H__ */ diff --git a/src/mesa/drivers/dri/radeon/radeon_lock.c b/src/mesa/drivers/dri/radeon/radeon_lock.c -index 64bb3ca..9a7e76b 100644 +index 64bb3ca..fb9e5e0 100644 --- a/src/mesa/drivers/dri/radeon/radeon_lock.c +++ b/src/mesa/drivers/dri/radeon/radeon_lock.c -@@ -41,12 +41,11 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +@@ -41,30 +41,13 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "main/glheader.h" #include "main/mtypes.h" @@ -27011,40 +27837,26 @@ index 64bb3ca..9a7e76b 100644 - #include "drirenderbuffer.h" - #if DEBUG_LOCKING -@@ -56,13 +55,28 @@ int prevLockLine = 0; - - /* Turn on/off page flipping according to the flags in the sarea: - */ +-#if DEBUG_LOCKING +-char *prevLockFile = NULL; +-int prevLockLine = 0; +-#endif +- +-/* Turn on/off page flipping according to the flags in the sarea: +- */ -static void radeonUpdatePageFlipping(radeonContextPtr rmesa) -+void radeonUpdatePageFlipping(radeonContextPtr rmesa) - { -+ int use_back; -+ __DRIdrawablePrivate *const drawable = rmesa->dri.drawable; -+ GLframebuffer *fb = drawable->driverPrivate; -+ - rmesa->doPageFlip = rmesa->sarea->pfState; - if (rmesa->glCtx->WinSysDrawBuffer) { +-{ +- rmesa->doPageFlip = rmesa->sarea->pfState; +- if (rmesa->glCtx->WinSysDrawBuffer) { - driFlipRenderbuffers(rmesa->glCtx->WinSysDrawBuffer, - rmesa->sarea->pfCurrentPage); -+ rmesa->vtbl.update_draw_buffer(rmesa->glCtx); - } -+ -+ use_back = rmesa->glCtx->DrawBuffer ? -+ (rmesa->glCtx->DrawBuffer->_ColorDrawBufferIndexes[0] == -+ BUFFER_BACK_LEFT) : 1; -+ use_back ^= (rmesa->sarea->pfCurrentPage == 1); -+ -+ if (use_back) -+ rmesa->state.color.rrb = (void *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; -+ else -+ rmesa->state.color.rrb = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; -+ -+ rmesa->state.depth.rrb = (void *)fb->Attachment[BUFFER_DEPTH].Renderbuffer; - } - +- } +-} +- /* Update the hardware state. This is called if another context has -@@ -80,6 +94,8 @@ void radeonGetLock(radeonContextPtr rmesa, GLuint flags) + * grabbed the hardware lock, which includes the X server. This + * function also updates the driver's window state after the X server +@@ -80,6 +63,8 @@ void radeonGetLock(radeonContextPtr rmesa, GLuint flags) __DRIscreenPrivate *sPriv = rmesa->dri.screen; drm_radeon_sarea_t *sarea = rmesa->sarea; @@ -27053,13 +27865,16 @@ index 64bb3ca..9a7e76b 100644 drmGetLock(rmesa->dri.fd, rmesa->dri.hwContext, flags); /* The window might have moved, so we might need to get new clip -@@ -98,27 +114,11 @@ void radeonGetLock(radeonContextPtr rmesa, GLuint flags) +@@ -96,29 +81,52 @@ void radeonGetLock(radeonContextPtr rmesa, GLuint flags) + } + if (rmesa->lastStamp != drawable->lastStamp) { - radeonUpdatePageFlipping(rmesa); - radeonSetCliprects(rmesa); +- radeonUpdatePageFlipping(rmesa); +- radeonSetCliprects(rmesa); - radeonUpdateViewportOffset(rmesa->glCtx); -+ rmesa->vtbl.update_viewport_offset(rmesa->glCtx); - driUpdateFramebufferSize(rmesa->glCtx, drawable); +- driUpdateFramebufferSize(rmesa->glCtx, drawable); ++ radeon_window_moved(rmesa); ++ rmesa->lastStamp = drawable->lastStamp; } - RADEON_STATECHANGE(rmesa, ctx); @@ -27070,24 +27885,63 @@ index 64bb3ca..9a7e76b 100644 - rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] &= - ~RADEON_COLOR_TILE_ENABLE; - } -- ++ rmesa->vtbl.get_lock(rmesa); + - if (sarea->ctx_owner != rmesa->dri.hwContext) { - int i; - sarea->ctx_owner = rmesa->dri.hwContext; -- ++ rmesa->lost_context = GL_TRUE; ++} + - for (i = 0; i < rmesa->nr_heaps; i++) { - DRI_AGE_TEXTURES(rmesa->texture_heaps[i]); - } -- } -+ rmesa->vtbl.get_lock(rmesa); ++static INLINE struct radeon_renderbuffer * ++radeon_get_renderbuffer(struct gl_framebuffer *fb, int attIndex) ++{ ++ if (attIndex >= 0) ++ return (struct radeon_renderbuffer *)fb->Attachment[attIndex].Renderbuffer; ++ else ++ return NULL; ++} ++ ++void radeon_lock_hardware(radeonContextPtr radeon) ++{ ++ __DRIdrawable *dPriv = radeon->dri.drawable; ++ char ret = 0; ++ struct radeon_framebuffer *rfb = NULL; ++ struct radeon_renderbuffer *rrb = NULL; ++ ++ if (radeon->dri.drawable) { ++ rfb = radeon->dri.drawable->driverPrivate; ++ ++ if (rfb) ++ rrb = radeon_get_renderbuffer(&rfb->base, ++ rfb->base._ColorDrawBufferIndexes[0]); + } - rmesa->lost_context = GL_TRUE; +- rmesa->lost_context = GL_TRUE; ++ if (!radeon->radeonScreen->driScreen->dri2.enabled) { ++ DRM_CAS(radeon->dri.hwLock, radeon->dri.hwContext, ++ (DRM_LOCK_HELD | radeon->dri.hwContext), ret ); ++ if (ret) ++ radeonGetLock(radeon, 0); ++ } ++} ++ ++void radeon_unlock_hardware(radeonContextPtr radeon) ++{ ++ if (!radeon->radeonScreen->driScreen->dri2.enabled) { ++ DRM_UNLOCK( radeon->dri.fd, ++ radeon->dri.hwLock, ++ radeon->dri.hwContext ); ++ } } diff --git a/src/mesa/drivers/dri/radeon/radeon_lock.h b/src/mesa/drivers/dri/radeon/radeon_lock.h -index 86e96aa..f5ebb8d 100644 +index 86e96aa..2817709 100644 --- a/src/mesa/drivers/dri/radeon/radeon_lock.h +++ b/src/mesa/drivers/dri/radeon/radeon_lock.h -@@ -39,8 +39,12 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +@@ -39,74 +39,21 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * Kevin E. Martin */ @@ -27095,44 +27949,81 @@ index 86e96aa..f5ebb8d 100644 -#define __RADEON_LOCK_H__ +#ifndef COMMON_LOCK_H +#define COMMON_LOCK_H -+ + +-extern void radeonGetLock(radeonContextPtr rmesa, GLuint flags); +- +-/* Turn DEBUG_LOCKING on to find locking conflicts. +- */ +-#define DEBUG_LOCKING 0 +- +-#if DEBUG_LOCKING +-extern char *prevLockFile; +-extern int prevLockLine; +- +-#define DEBUG_LOCK() \ +- do { \ +- prevLockFile = (__FILE__); \ +- prevLockLine = (__LINE__); \ +- } while (0) +- +-#define DEBUG_RESET() \ +- do { \ +- prevLockFile = 0; \ +- prevLockLine = 0; \ +- } while (0) +- +-#define DEBUG_CHECK_LOCK() \ +- do { \ +- if ( prevLockFile ) { \ +- fprintf( stderr, \ +- "LOCK SET!\n\tPrevious %s:%d\n\tCurrent: %s:%d\n", \ +- prevLockFile, prevLockLine, __FILE__, __LINE__ ); \ +- exit( 1 ); \ +- } \ +- } while (0) +- +-#else +#include "main/colormac.h" +#include "radeon_screen.h" +#include "radeon_common.h" - extern void radeonGetLock(radeonContextPtr rmesa, GLuint flags); +-#define DEBUG_LOCK() +-#define DEBUG_RESET() +-#define DEBUG_CHECK_LOCK() ++extern void radeonGetLock(radeonContextPtr rmesa, GLuint flags); -@@ -94,19 +98,23 @@ extern int prevLockLine; - do { \ - char __ret = 0; \ - DEBUG_CHECK_LOCK(); \ +-#endif +- +-/* +- * !!! We may want to separate locks from locks with validation. This +- * could be used to improve performance for those things commands that +- * do not do any drawing !!! +- */ ++void radeon_lock_hardware(radeonContextPtr rmesa); ++void radeon_unlock_hardware(radeonContextPtr rmesa); + + /* Lock the hardware and validate our state. + */ +-#define LOCK_HARDWARE( rmesa ) \ +- do { \ +- char __ret = 0; \ +- DEBUG_CHECK_LOCK(); \ - DRM_CAS( (rmesa)->dri.hwLock, (rmesa)->dri.hwContext, \ - (DRM_LOCK_HELD | (rmesa)->dri.hwContext), __ret ); \ - if ( __ret ) \ - radeonGetLock( (rmesa), 0 ); \ - DEBUG_LOCK(); \ -+ if (!(rmesa)->radeonScreen->driScreen->dri2.enabled) { \ -+ DRM_CAS( (rmesa)->dri.hwLock, (rmesa)->dri.hwContext, \ -+ (DRM_LOCK_HELD | (rmesa)->dri.hwContext), __ret ); \ -+ if ( __ret ) \ -+ radeonGetLock( (rmesa), 0 ); \ -+ } \ -+ DEBUG_LOCK(); \ - } while (0) - - #define UNLOCK_HARDWARE( rmesa ) \ - do { \ +- } while (0) +- +-#define UNLOCK_HARDWARE( rmesa ) \ +- do { \ - DRM_UNLOCK( (rmesa)->dri.fd, \ - (rmesa)->dri.hwLock, \ - (rmesa)->dri.hwContext ); \ - DEBUG_RESET(); \ -+ if (!(rmesa)->radeonScreen->driScreen->dri2.enabled) { \ -+ DRM_UNLOCK( (rmesa)->dri.fd, \ -+ (rmesa)->dri.hwLock, \ -+ (rmesa)->dri.hwContext ); \ -+ DEBUG_RESET(); \ -+ } \ - } while (0) +- } while (0) ++#define LOCK_HARDWARE( rmesa ) radeon_lock_hardware(rmesa) ++#define UNLOCK_HARDWARE( rmesa ) radeon_unlock_hardware(rmesa) -#endif /* __RADEON_LOCK_H__ */ +#endif @@ -28333,7 +29224,7 @@ index 1ec06bc..f30eb1c 100644 drm_clip_rect_t *boxes ); diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c -index e3afaa9..c591e9f 100644 +index e3afaa9..e90dffd 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -35,6 +35,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. @@ -28445,7 +29336,31 @@ index e3afaa9..c591e9f 100644 static const struct dri_debug_control debug_control[] = { {"fall", DEBUG_FALLBACKS}, -@@ -349,137 +356,17 @@ static const __DRItexOffsetExtension r300texOffsetExtension = { +@@ -328,6 +335,11 @@ static const __DRItexOffsetExtension radeonTexOffsetExtension = { + { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, + radeonSetTexOffset, + }; ++ ++static const __DRItexBufferExtension radeonTexBufferExtension = { ++ { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION }, ++ radeonSetTexBuffer, ++}; + #endif + + #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) +@@ -342,6 +354,11 @@ static const __DRItexOffsetExtension r200texOffsetExtension = { + { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, + r200SetTexOffset, + }; ++ ++static const __DRItexBufferExtension r200TexBufferExtension = { ++ { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION }, ++ r200SetTexBuffer, ++}; + #endif + + #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) +@@ -349,137 +366,17 @@ static const __DRItexOffsetExtension r300texOffsetExtension = { { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, r300SetTexOffset, }; @@ -28467,7 +29382,7 @@ index e3afaa9..c591e9f 100644 - fprintf(stderr,"\nERROR! sizeof(RADEONDRIRec) does not match passed size from device driver\n"); - return GL_FALSE; - } - +- - /* Allocate the private area */ - screen = (radeonScreenPtr) CALLOC( sizeof(*screen) ); - if ( !screen ) { @@ -28475,7 +29390,7 @@ index e3afaa9..c591e9f 100644 - __FUNCTION__); - return NULL; - } -- + -#if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) - RADEON_DEBUG = driParseDebugString(getenv("RADEON_DEBUG"), debug_control); +static const __DRItexBufferExtension r300TexBufferExtension = { @@ -28590,20 +29505,7 @@ index e3afaa9..c591e9f 100644 case PCI_CHIP_RADEON_LY: case PCI_CHIP_RADEON_LZ: case PCI_CHIP_RADEON_QY: -@@ -683,12 +570,6 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) - screen->chip_family = CHIP_FAMILY_RS400; - break; - -- case PCI_CHIP_RS600_793F: -- case PCI_CHIP_RS600_7941: -- case PCI_CHIP_RS600_7942: -- screen->chip_family = CHIP_FAMILY_RS600; -- break; -- - case PCI_CHIP_RS690_791E: - case PCI_CHIP_RS690_791F: - screen->chip_family = CHIP_FAMILY_RS690; -@@ -817,9 +698,162 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) +@@ -817,9 +714,162 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) default: fprintf(stderr, "unknown chip id 0x%x, can't guess.\n", @@ -28767,25 +29669,16 @@ index e3afaa9..c591e9f 100644 if ((screen->chip_family == CHIP_FAMILY_R350 || screen->chip_family == CHIP_FAMILY_R300) && sPriv->ddx_version.minor < 2) { fprintf(stderr, "xf86-video-ati-6.6.2 or newer needed for Radeon 9500/9700/9800 cards.\n"); -@@ -847,7 +881,7 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) +@@ -847,7 +897,7 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) ret = radeonGetParam( sPriv->fd, RADEON_PARAM_FB_LOCATION, &temp); if (ret) { - if (screen->chip_family < CHIP_FAMILY_RS600) -+ if (screen->chip_family < CHIP_FAMILY_RS690 && !screen->kernel_mm) ++ if (screen->chip_family < CHIP_FAMILY_RS600 && !screen->kernel_mm) screen->fbLocation = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff) << 16; else { FREE( screen ); -@@ -858,7 +892,7 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) - screen->fbLocation = (temp & 0xffff) << 16; - } - -- if (screen->chip_family >= CHIP_FAMILY_R300) { -+ if (screen->chip_family >= CHIP_FAMILY_RV515) { - ret = radeonGetParam( sPriv->fd, RADEON_PARAM_NUM_GB_PIPES, - &temp); - if (ret) { -@@ -949,6 +983,103 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) +@@ -949,26 +999,127 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) screen->extensions[i++] = &driMediaStreamCounterExtension.base; } @@ -28887,14 +29780,20 @@ index e3afaa9..c591e9f 100644 + } + #if !RADEON_COMMON - screen->extensions[i++] = &radeonTexOffsetExtension.base; +- screen->extensions[i++] = &radeonTexOffsetExtension.base; ++ screen->extensions[i++] = &radeonTexBufferExtension.base; #endif -@@ -961,14 +1092,19 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) + + #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) + if (IS_R200_CLASS(screen)) + screen->extensions[i++] = &r200AllocateExtension.base; + +- screen->extensions[i++] = &r200texOffsetExtension.base; ++ screen->extensions[i++] = &r200TexBufferExtension.base; #endif #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) - screen->extensions[i++] = &r300texOffsetExtension.base; -+ //screen->extensions[i++] = &r300texOffsetExtension.base; + screen->extensions[i++] = &r300TexBufferExtension.base; #endif @@ -28911,7 +29810,7 @@ index e3afaa9..c591e9f 100644 return screen; } -@@ -977,23 +1113,32 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) +@@ -977,23 +1128,32 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) static void radeonDestroyScreen( __DRIscreenPrivate *sPriv ) { @@ -28957,7 +29856,7 @@ index e3afaa9..c591e9f 100644 } -@@ -1002,15 +1147,102 @@ radeonDestroyScreen( __DRIscreenPrivate *sPriv ) +@@ -1002,15 +1162,102 @@ radeonDestroyScreen( __DRIscreenPrivate *sPriv ) static GLboolean radeonInitDriver( __DRIscreenPrivate *sPriv ) { @@ -29066,12 +29965,26 @@ index e3afaa9..c591e9f 100644 /** * Create the Mesa framebuffer and renderbuffers for a given window/drawable. -@@ -1026,95 +1258,86 @@ radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv, +@@ -1024,97 +1271,93 @@ radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv, + const __GLcontextModes *mesaVis, + GLboolean isPixmap ) { - radeonScreenPtr screen = (radeonScreenPtr) driScrnPriv->private; - +- radeonScreenPtr screen = (radeonScreenPtr) driScrnPriv->private; +- - if (isPixmap) { -- return GL_FALSE; /* not implemented */ ++ radeonScreenPtr screen = (radeonScreenPtr) driScrnPriv->private; ++ ++ const GLboolean swDepth = GL_FALSE; ++ const GLboolean swAlpha = GL_FALSE; ++ const GLboolean swAccum = mesaVis->accumRedBits > 0; ++ const GLboolean swStencil = mesaVis->stencilBits > 0 && ++ mesaVis->depthBits != 24; ++ GLenum rgbFormat = (mesaVis->redBits == 5 ? GL_RGB5 : GL_RGBA8); ++ GLenum depthFormat = GL_NONE; ++ struct radeon_framebuffer *rfb; ++ ++ if (isPixmap) + return GL_FALSE; /* not implemented */ - } - else { - const GLboolean swDepth = GL_FALSE; @@ -29092,27 +30005,6 @@ index e3afaa9..c591e9f 100644 - radeonSetSpanFunctions(frontRb, mesaVis); - _mesa_add_renderbuffer(fb, BUFFER_FRONT_LEFT, &frontRb->Base); - } -+ const GLboolean swDepth = GL_FALSE; -+ const GLboolean swAlpha = GL_FALSE; -+ const GLboolean swAccum = mesaVis->accumRedBits > 0; -+ const GLboolean swStencil = mesaVis->stencilBits > 0 && -+ mesaVis->depthBits != 24; -+ GLenum rgbFormat = (mesaVis->redBits == 5 ? GL_RGB5 : GL_RGBA8); -+ GLenum depthFormat = GL_NONE; -+ struct gl_framebuffer *fb = _mesa_create_framebuffer(mesaVis); -+ -+ if (mesaVis->depthBits == 16) -+ depthFormat = GL_DEPTH_COMPONENT16; -+ else if (mesaVis->depthBits == 24) -+ depthFormat = GL_DEPTH_COMPONENT24; -+ -+ /* front color renderbuffer */ -+ { -+ struct radeon_renderbuffer *front = -+ radeon_create_renderbuffer(rgbFormat, driDrawPriv); -+ _mesa_add_renderbuffer(fb, BUFFER_FRONT_LEFT, &front->base); -+ front->has_surface = 1; -+ } - /* back color renderbuffer */ - if (mesaVis->doubleBufferMode) { @@ -29125,13 +30017,9 @@ index e3afaa9..c591e9f 100644 - radeonSetSpanFunctions(backRb, mesaVis); - _mesa_add_renderbuffer(fb, BUFFER_BACK_LEFT, &backRb->Base); - } -+ /* back color renderbuffer */ -+ if (mesaVis->doubleBufferMode) { -+ struct radeon_renderbuffer *back = -+ radeon_create_renderbuffer(rgbFormat, driDrawPriv); -+ _mesa_add_renderbuffer(fb, BUFFER_BACK_LEFT, &back->base); -+ back->has_surface = 1; -+ } ++ rfb = CALLOC_STRUCT(radeon_framebuffer); ++ if (!rfb) ++ return GL_FALSE; - /* depth renderbuffer */ - if (mesaVis->depthBits == 16) { @@ -29156,13 +30044,7 @@ index e3afaa9..c591e9f 100644 - _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthRb->Base); - depthRb->depthHasSurface = screen->depthHasSurface; - } -+ /* depth renderbuffer */ -+ if (depthFormat != GL_NONE) { -+ struct radeon_renderbuffer *depth = -+ radeon_create_renderbuffer(depthFormat, driDrawPriv); -+ _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depth->base); -+ depth->has_surface = screen->depthHasSurface; -+ } ++ _mesa_initialize_framebuffer(&rfb->base, mesaVis); - /* stencil renderbuffer */ - if (mesaVis->stencilBits > 0 && !swStencil) { @@ -29176,13 +30058,10 @@ index e3afaa9..c591e9f 100644 - _mesa_add_renderbuffer(fb, BUFFER_STENCIL, &stencilRb->Base); - stencilRb->depthHasSurface = screen->depthHasSurface; - } -+ /* stencil renderbuffer */ -+ if (mesaVis->stencilBits > 0 && !swStencil) { -+ struct radeon_renderbuffer *stencil = -+ radeon_create_renderbuffer(GL_STENCIL_INDEX8_EXT, driDrawPriv); -+ _mesa_add_renderbuffer(fb, BUFFER_STENCIL, &stencil->base); -+ stencil->has_surface = screen->depthHasSurface; -+ } ++ if (mesaVis->depthBits == 16) ++ depthFormat = GL_DEPTH_COMPONENT16; ++ else if (mesaVis->depthBits == 24) ++ depthFormat = GL_DEPTH_COMPONENT24; - _mesa_add_soft_renderbuffers(fb, - GL_FALSE, /* color */ @@ -29192,39 +30071,67 @@ index e3afaa9..c591e9f 100644 - swAlpha, - GL_FALSE /* aux */); - driDrawPriv->driverPrivate = (void *) fb; -+ _mesa_add_soft_renderbuffers(fb, ++ /* front color renderbuffer */ ++ rfb->color_rb[0] = radeon_create_renderbuffer(rgbFormat, driDrawPriv); ++ _mesa_add_renderbuffer(&rfb->base, BUFFER_FRONT_LEFT, &rfb->color_rb[0]->base); ++ rfb->color_rb[0]->has_surface = 1; + +- return (driDrawPriv->driverPrivate != NULL); +- } +-} ++ /* back color renderbuffer */ ++ if (mesaVis->doubleBufferMode) { ++ rfb->color_rb[1] = radeon_create_renderbuffer(rgbFormat, driDrawPriv); ++ _mesa_add_renderbuffer(&rfb->base, BUFFER_BACK_LEFT, &rfb->color_rb[1]->base); ++ rfb->color_rb[1]->has_surface = 1; ++ } + ++ /* depth renderbuffer */ ++ if (depthFormat != GL_NONE) { ++ struct radeon_renderbuffer *depth = ++ radeon_create_renderbuffer(depthFormat, driDrawPriv); ++ _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depth->base); ++ depth->has_surface = screen->depthHasSurface; ++ } ++ ++ /* stencil renderbuffer */ ++ if (mesaVis->stencilBits > 0 && !swStencil) { ++ struct radeon_renderbuffer *stencil = ++ radeon_create_renderbuffer(GL_STENCIL_INDEX8_EXT, driDrawPriv); ++ _mesa_add_renderbuffer(&rfb->base, BUFFER_STENCIL, &stencil->base); ++ stencil->has_surface = screen->depthHasSurface; ++ } ++ ++ _mesa_add_soft_renderbuffers(&rfb->base, + GL_FALSE, /* color */ + swDepth, + swStencil, + swAccum, + swAlpha, + GL_FALSE /* aux */); -+ driDrawPriv->driverPrivate = (void *) fb; - -- return (driDrawPriv->driverPrivate != NULL); -- } ++ driDrawPriv->driverPrivate = (void *) rfb; ++ + return (driDrawPriv->driverPrivate != NULL); - } ++} -- static void radeonDestroyBuffer(__DRIdrawablePrivate *driDrawPriv) { -+ struct radeon_renderbuffer *rb; -+ GLframebuffer *fb; ++ struct radeon_renderbuffer *rb; ++ struct radeon_framebuffer *rfb; + -+ fb = (void*)driDrawPriv->driverPrivate; -+ rb = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; ++ rfb = (void*)driDrawPriv->driverPrivate; ++ rb = (void *)rfb->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer; + if (rb && rb->bo) { + radeon_bo_unref(rb->bo); + rb->bo = NULL; + } -+ rb = (void *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; ++ rb = (void *)rfb->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer; + if (rb && rb->bo) { + radeon_bo_unref(rb->bo); + rb->bo = NULL; + } -+ rb = (void *)fb->Attachment[BUFFER_DEPTH].Renderbuffer; ++ rb = (void *)rfb->base.Attachment[BUFFER_DEPTH].Renderbuffer; + if (rb && rb->bo) { + radeon_bo_unref(rb->bo); + rb->bo = NULL; @@ -29232,7 +30139,7 @@ index e3afaa9..c591e9f 100644 _mesa_unreference_framebuffer((GLframebuffer **)(&(driDrawPriv->driverPrivate))); } -@@ -1149,6 +1372,7 @@ static void radeonDestroyContext(__DRIcontextPrivate * driContextPriv) +@@ -1149,6 +1392,7 @@ static void radeonDestroyContext(__DRIcontextPrivate * driContextPriv) #endif @@ -29240,7 +30147,7 @@ index e3afaa9..c591e9f 100644 /** * This is the driver specific part of the createNewScreen entry point. * -@@ -1201,18 +1425,109 @@ radeonInitScreen(__DRIscreenPrivate *psp) +@@ -1201,18 +1445,109 @@ radeonInitScreen(__DRIscreenPrivate *psp) driInitSingleExtension( NULL, NV_vp_extension ); driInitSingleExtension( NULL, ATI_fs_extension ); driInitExtensions( NULL, point_extensions, GL_FALSE ); @@ -29260,7 +30167,7 @@ index e3afaa9..c591e9f 100644 + (dri_priv->bpp == 16) ? 0 : 8, 1); } +#define ARRAY_SIZE(a) (sizeof (a) / sizeof ((a)[0])) - ++ +/** + * This is the driver specific part of the createNewScreen entry point. + * Called when using DRI2. @@ -29300,7 +30207,7 @@ index e3afaa9..c591e9f 100644 + driInitSingleExtension( NULL, ATI_fs_extension ); + driInitExtensions( NULL, point_extensions, GL_FALSE ); +#endif -+ + + if (!radeonInitDriver(psp)) { + return NULL; + } @@ -29352,19 +30259,43 @@ index e3afaa9..c591e9f 100644 /** * Get information about previous buffer swaps. -@@ -1220,11 +1535,7 @@ radeonInitScreen(__DRIscreenPrivate *psp) +@@ -1220,25 +1555,21 @@ radeonInitScreen(__DRIscreenPrivate *psp) static int getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo ) { -#if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)) - radeonContextPtr rmesa; +- radeonContextPtr rmesa; -#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) - r200ContextPtr rmesa; -#endif ++ struct radeon_framebuffer *rfb; - if ( (dPriv == NULL) || (dPriv->driContextPriv == NULL) - || (dPriv->driContextPriv->driverPrivate == NULL) -@@ -1261,6 +1572,8 @@ const struct __DriverAPIRec driDriverAPI = { +- if ( (dPriv == NULL) || (dPriv->driContextPriv == NULL) +- || (dPriv->driContextPriv->driverPrivate == NULL) +- || (sInfo == NULL) ) { +- return -1; ++ if ( (dPriv == NULL) || (dPriv->driContextPriv == NULL) ++ || (dPriv->driContextPriv->driverPrivate == NULL) ++ || (sInfo == NULL) ) { ++ return -1; + } + +- rmesa = dPriv->driContextPriv->driverPrivate; +- sInfo->swap_count = rmesa->swap_count; +- sInfo->swap_ust = rmesa->swap_ust; +- sInfo->swap_missed_count = rmesa->swap_missed_count; ++ rfb = dPriv->driverPrivate; ++ sInfo->swap_count = rfb->swap_count; ++ sInfo->swap_ust = rfb->swap_ust; ++ sInfo->swap_missed_count = rfb->swap_missed_count; + + sInfo->swap_missed_usage = (sInfo->swap_missed_count != 0) +- ? driCalculateSwapUsage( dPriv, 0, rmesa->swap_missed_ust ) ++ ? driCalculateSwapUsage( dPriv, 0, rfb->swap_missed_ust ) + : 0.0; + + return 0; +@@ -1261,6 +1592,8 @@ const struct __DriverAPIRec driDriverAPI = { .WaitForSBC = NULL, .SwapBuffersMSC = NULL, .CopySubBuffer = radeonCopySubBuffer, @@ -29373,7 +30304,7 @@ index e3afaa9..c591e9f 100644 }; #else const struct __DriverAPIRec driDriverAPI = { -@@ -1270,14 +1583,16 @@ const struct __DriverAPIRec driDriverAPI = { +@@ -1270,14 +1603,16 @@ const struct __DriverAPIRec driDriverAPI = { .DestroyContext = r200DestroyContext, .CreateBuffer = radeonCreateBuffer, .DestroyBuffer = radeonDestroyBuffer, @@ -29937,7 +30868,7 @@ index 9abe086..dd44ab5 100644 +extern void radeonSetSpanFunctions(struct radeon_renderbuffer *rrb); #endif diff --git a/src/mesa/drivers/dri/radeon/radeon_state.c b/src/mesa/drivers/dri/radeon/radeon_state.c -index 32bcff3..5fffa28 100644 +index 32bcff3..42b65cb 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state.c +++ b/src/mesa/drivers/dri/radeon/radeon_state.c @@ -62,7 +62,7 @@ static void radeonUpdateSpecular( GLcontext *ctx ); @@ -30382,7 +31313,7 @@ index 32bcff3..5fffa28 100644 ((GLuint) (ctx->Stencil.Clear & 0xff) | (0xff << RADEON_STENCIL_MASK_SHIFT) | ((ctx->Stencil.WriteMask[0] & 0xff) << RADEON_STENCIL_WRITEMASK_SHIFT)); -@@ -1481,20 +1385,20 @@ static void radeonClearStencil( GLcontext *ctx, GLint s ) +@@ -1481,20 +1385,19 @@ static void radeonClearStencil( GLcontext *ctx, GLint s ) */ void radeonUpdateWindow( GLcontext *ctx ) { @@ -30406,11 +31337,19 @@ index 32bcff3..5fffa28 100644 + float_ui32_type tz = { v[MAT_TZ] * rmesa->radeon.state.depth.scale }; - RADEON_FIREVERTICES( rmesa ); -+ radeon_firevertices(&rmesa->radeon); RADEON_STATECHANGE( rmesa, vpt ); rmesa->hw.vpt.cmd[VPT_SE_VPORT_XSCALE] = sx.ui32; -@@ -1524,8 +1428,8 @@ static void radeonDepthRange( GLcontext *ctx, GLclampd nearval, +@@ -1514,6 +1417,8 @@ static void radeonViewport( GLcontext *ctx, GLint x, GLint y, + * values, or keep the originals hanging around. + */ + radeonUpdateWindow( ctx ); ++ ++ radeon_viewport(ctx, x, y, width, height); + } + + static void radeonDepthRange( GLcontext *ctx, GLclampd nearval, +@@ -1524,8 +1429,8 @@ static void radeonDepthRange( GLcontext *ctx, GLclampd nearval, void radeonUpdateViewportOffset( GLcontext *ctx ) { @@ -30421,7 +31360,7 @@ index 32bcff3..5fffa28 100644 GLfloat xoffset = (GLfloat)dPriv->x; GLfloat yoffset = (GLfloat)dPriv->y + dPriv->h; const GLfloat *v = ctx->Viewport._WindowMap.m; -@@ -1555,8 +1459,8 @@ void radeonUpdateViewportOffset( GLcontext *ctx ) +@@ -1555,8 +1460,8 @@ void radeonUpdateViewportOffset( GLcontext *ctx ) RADEON_STIPPLE_Y_OFFSET_MASK); /* add magic offsets, then invert */ @@ -30432,7 +31371,7 @@ index 32bcff3..5fffa28 100644 & RADEON_STIPPLE_COORD_MASK); m |= ((stx << RADEON_STIPPLE_X_OFFSET_SHIFT) | -@@ -1580,20 +1484,20 @@ void radeonUpdateViewportOffset( GLcontext *ctx ) +@@ -1580,20 +1485,20 @@ void radeonUpdateViewportOffset( GLcontext *ctx ) static void radeonClearColor( GLcontext *ctx, const GLfloat color[4] ) { @@ -30456,7 +31395,7 @@ index 32bcff3..5fffa28 100644 FALLBACK( rmesa, RADEON_FALLBACK_RENDER_MODE, (mode != GL_RENDER) ); } -@@ -1619,7 +1523,7 @@ static GLuint radeon_rop_tab[] = { +@@ -1619,7 +1524,7 @@ static GLuint radeon_rop_tab[] = { static void radeonLogicOpCode( GLcontext *ctx, GLenum opcode ) { @@ -30465,10 +31404,12 @@ index 32bcff3..5fffa28 100644 GLuint rop = (GLuint)opcode - GL_CLEAR; ASSERT( rop < 16 ); -@@ -1630,66 +1534,17 @@ static void radeonLogicOpCode( GLcontext *ctx, GLenum opcode ) +@@ -1628,105 +1533,13 @@ static void radeonLogicOpCode( GLcontext *ctx, GLenum opcode ) + rmesa->hw.msk.cmd[MSK_RB3D_ROPCNTL] = radeon_rop_tab[rop]; + } - - /** +- +-/** - * Set up the cliprects for either front or back-buffer drawing. - */ -void radeonSetCliprects( radeonContextPtr rmesa ) @@ -30518,35 +31459,50 @@ index 32bcff3..5fffa28 100644 - - -/** - * Called via glDrawBuffer. - */ - static void radeonDrawBuffer( GLcontext *ctx, GLenum mode ) - { +- * Called via glDrawBuffer. +- */ +-static void radeonDrawBuffer( GLcontext *ctx, GLenum mode ) +-{ - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); -+ r100ContextPtr rmesa = R100_CONTEXT(ctx); - - if (RADEON_DEBUG & DEBUG_DRI) - fprintf(stderr, "%s %s\n", __FUNCTION__, - _mesa_lookup_enum_by_nr( mode )); - +- +- if (RADEON_DEBUG & DEBUG_DRI) +- fprintf(stderr, "%s %s\n", __FUNCTION__, +- _mesa_lookup_enum_by_nr( mode )); +- - RADEON_FIREVERTICES(rmesa); /* don't pipeline cliprect changes */ -+ radeon_firevertices(&rmesa->radeon); /* don't pipeline cliprect changes */ - - if (ctx->DrawBuffer->_NumColorDrawBuffers != 1) { - /* 0 (GL_NONE) buffers or multiple color drawing buffers */ -@@ -1707,8 +1562,9 @@ static void radeonDrawBuffer( GLcontext *ctx, GLenum mode ) - return; - } - +- +- if (ctx->DrawBuffer->_NumColorDrawBuffers != 1) { +- /* 0 (GL_NONE) buffers or multiple color drawing buffers */ +- FALLBACK( rmesa, RADEON_FALLBACK_DRAW_BUFFER, GL_TRUE ); +- return; +- } +- +- switch ( ctx->DrawBuffer->_ColorDrawBufferIndexes[0] ) { +- case BUFFER_FRONT_LEFT: +- case BUFFER_BACK_LEFT: +- FALLBACK( rmesa, RADEON_FALLBACK_DRAW_BUFFER, GL_FALSE ); +- break; +- default: +- FALLBACK( rmesa, RADEON_FALLBACK_DRAW_BUFFER, GL_TRUE ); +- return; +- } +- - radeonSetCliprects( rmesa ); - -+ radeonSetCliprects( &rmesa->radeon ); -+ if (!rmesa->radeon.radeonScreen->driScreen->dri2.enabled) -+ radeonUpdatePageFlipping(&rmesa->radeon); - /* We'll set the drawing engine's offset/pitch parameters later - * when we update other state. - */ -@@ -1726,7 +1582,7 @@ static void radeonReadBuffer( GLcontext *ctx, GLenum mode ) +- /* We'll set the drawing engine's offset/pitch parameters later +- * when we update other state. +- */ +-} +- +-static void radeonReadBuffer( GLcontext *ctx, GLenum mode ) +-{ +- /* nothing, until we implement h/w glRead/CopyPixels or CopyTexImage */ +-} +- +- + /* ============================================================= + * State enable/disable + */ static void radeonEnable( GLcontext *ctx, GLenum cap, GLboolean state ) { @@ -30555,7 +31511,7 @@ index 32bcff3..5fffa28 100644 GLuint p, flag; if ( RADEON_DEBUG & DEBUG_STATE ) -@@ -1821,10 +1677,10 @@ static void radeonEnable( GLcontext *ctx, GLenum cap, GLboolean state ) +@@ -1821,10 +1634,10 @@ static void radeonEnable( GLcontext *ctx, GLenum cap, GLboolean state ) RADEON_STATECHANGE(rmesa, ctx ); if ( state ) { rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_ENABLE; @@ -30568,7 +31524,7 @@ index 32bcff3..5fffa28 100644 } break; -@@ -1971,13 +1827,13 @@ static void radeonEnable( GLcontext *ctx, GLenum cap, GLboolean state ) +@@ -1971,13 +1784,13 @@ static void radeonEnable( GLcontext *ctx, GLenum cap, GLboolean state ) } case GL_SCISSOR_TEST: @@ -30585,7 +31541,7 @@ index 32bcff3..5fffa28 100644 RADEON_STATECHANGE( rmesa, ctx ); if ( state ) { rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_STENCIL_ENABLE; -@@ -2010,7 +1866,7 @@ static void radeonEnable( GLcontext *ctx, GLenum cap, GLboolean state ) +@@ -2010,7 +1823,7 @@ static void radeonEnable( GLcontext *ctx, GLenum cap, GLboolean state ) static void radeonLightingSpaceChange( GLcontext *ctx ) { @@ -30594,7 +31550,7 @@ index 32bcff3..5fffa28 100644 GLboolean tmp; RADEON_STATECHANGE( rmesa, tcl ); -@@ -2039,7 +1895,7 @@ static void radeonLightingSpaceChange( GLcontext *ctx ) +@@ -2039,7 +1852,7 @@ static void radeonLightingSpaceChange( GLcontext *ctx ) */ @@ -30603,7 +31559,7 @@ index 32bcff3..5fffa28 100644 int unit, GLboolean swapcols ) { /* Here's how this works: on r100, only 3 tex coords can be submitted, so the -@@ -2065,7 +1921,7 @@ void radeonUploadTexMatrix( radeonContextPtr rmesa, +@@ -2065,7 +1878,7 @@ void radeonUploadTexMatrix( radeonContextPtr rmesa, int idx = TEXMAT_0 + unit; float *dest = ((float *)RADEON_DB_STATE( mat[idx] )) + MAT_ELT_0; int i; @@ -30612,7 +31568,7 @@ index 32bcff3..5fffa28 100644 GLfloat *src = rmesa->tmpmat[unit].m; rmesa->TexMatColSwap &= ~(1 << unit); -@@ -2119,7 +1975,7 @@ void radeonUploadTexMatrix( radeonContextPtr rmesa, +@@ -2119,7 +1932,7 @@ void radeonUploadTexMatrix( radeonContextPtr rmesa, } @@ -30621,7 +31577,7 @@ index 32bcff3..5fffa28 100644 { float *dest = ((float *)RADEON_DB_STATE( mat[idx] ))+MAT_ELT_0; int i; -@@ -2135,7 +1991,7 @@ static void upload_matrix( radeonContextPtr rmesa, GLfloat *src, int idx ) +@@ -2135,7 +1948,7 @@ static void upload_matrix( radeonContextPtr rmesa, GLfloat *src, int idx ) RADEON_DB_STATECHANGE( rmesa, &rmesa->hw.mat[idx] ); } @@ -30630,7 +31586,7 @@ index 32bcff3..5fffa28 100644 { float *dest = ((float *)RADEON_DB_STATE( mat[idx] ))+MAT_ELT_0; memcpy(dest, src, 16*sizeof(float)); -@@ -2145,7 +2001,7 @@ static void upload_matrix_t( radeonContextPtr rmesa, GLfloat *src, int idx ) +@@ -2145,7 +1958,7 @@ static void upload_matrix_t( radeonContextPtr rmesa, GLfloat *src, int idx ) static void update_texturematrix( GLcontext *ctx ) { @@ -30639,17 +31595,22 @@ index 32bcff3..5fffa28 100644 GLuint tpc = rmesa->hw.tcl.cmd[TCL_TEXTURE_PROC_CTL]; GLuint vs = rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXSEL]; int unit; -@@ -2217,43 +2073,32 @@ static void update_texturematrix( GLcontext *ctx ) - void - radeonUpdateDrawBuffer(GLcontext *ctx) - { -- radeonContextPtr rmesa = RADEON_CONTEXT(ctx); -+ r100ContextPtr rmesa = R100_CONTEXT(ctx); - struct gl_framebuffer *fb = ctx->DrawBuffer; -- driRenderbuffer *drb; -+ struct radeon_renderbuffer *rrb; +@@ -2210,58 +2023,21 @@ static void update_texturematrix( GLcontext *ctx ) + } - if (fb->_ColorDrawBufferIndexes[0] == BUFFER_FRONT_LEFT) { + +-/** +- * Tell the card where to render (offset, pitch). +- * Effected by glDrawBuffer, etc +- */ +-void +-radeonUpdateDrawBuffer(GLcontext *ctx) +-{ +- radeonContextPtr rmesa = RADEON_CONTEXT(ctx); +- struct gl_framebuffer *fb = ctx->DrawBuffer; +- driRenderbuffer *drb; +- +- if (fb->_ColorDrawBufferIndexes[0] == BUFFER_FRONT_LEFT) { - /* draw to front */ - drb = (driRenderbuffer *) fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; - } @@ -30660,22 +31621,12 @@ index 32bcff3..5fffa28 100644 - else { - /* drawing to multiple buffers, or none */ - return; -+ /* draw to front */ -+ rrb = (void *) fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; -+ } else if (fb->_ColorDrawBufferIndexes[0] == BUFFER_BACK_LEFT) { -+ /* draw to back */ -+ rrb = (void *) fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; -+ } else { -+ /* drawing to multiple buffers, or none */ -+ return; - } - +- } +- - assert(drb); - assert(drb->flippedPitch); -+ assert(rrb); -+ assert(rrb->pitch); - - RADEON_STATECHANGE( rmesa, ctx ); +- +- RADEON_STATECHANGE( rmesa, ctx ); - - /* Note: we used the (possibly) page-flipped values */ - rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] @@ -30685,9 +31636,9 @@ index 32bcff3..5fffa28 100644 - if (rmesa->sarea->tiling_enabled) { - rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= RADEON_COLOR_TILE_ENABLE; - } - } - - +-} +- +- void radeonValidateState( GLcontext *ctx ) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); @@ -30696,8 +31647,12 @@ index 32bcff3..5fffa28 100644 + GLuint new_state = rmesa->radeon.NewGLState; if (new_state & (_NEW_BUFFERS | _NEW_COLOR | _NEW_PIXEL)) { - radeonUpdateDrawBuffer(ctx); -@@ -2261,7 +2106,7 @@ void radeonValidateState( GLcontext *ctx ) +- radeonUpdateDrawBuffer(ctx); ++ _mesa_update_framebuffer(ctx); ++ /* this updates the DrawBuffer's Width/Height if it's a FBO */ ++ _mesa_update_draw_buffer_bounds(ctx); ++ RADEON_STATECHANGE(rmesa, ctx); + } if (new_state & _NEW_TEXTURE) { radeonUpdateTextureState( ctx ); @@ -30706,7 +31661,7 @@ index 32bcff3..5fffa28 100644 } /* Need an event driven matrix update? -@@ -2295,7 +2140,7 @@ void radeonValidateState( GLcontext *ctx ) +@@ -2295,7 +2071,7 @@ void radeonValidateState( GLcontext *ctx ) } @@ -30715,7 +31670,7 @@ index 32bcff3..5fffa28 100644 } -@@ -2306,7 +2151,7 @@ static void radeonInvalidateState( GLcontext *ctx, GLuint new_state ) +@@ -2306,7 +2082,7 @@ static void radeonInvalidateState( GLcontext *ctx, GLuint new_state ) _vbo_InvalidateState( ctx, new_state ); _tnl_InvalidateState( ctx, new_state ); _ae_invalidate_state( ctx, new_state ); @@ -30724,7 +31679,7 @@ index 32bcff3..5fffa28 100644 } -@@ -2330,15 +2175,15 @@ static GLboolean check_material( GLcontext *ctx ) +@@ -2330,15 +2106,15 @@ static GLboolean check_material( GLcontext *ctx ) static void radeonWrapRunPipeline( GLcontext *ctx ) { @@ -30783,7 +31738,7 @@ index 2171879..17c2b11 100644 diff --git a/src/mesa/drivers/dri/radeon/radeon_state_init.c b/src/mesa/drivers/dri/radeon/radeon_state_init.c -index 57dc380..7ff0eb4 100644 +index 57dc380..8b6caf1 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state_init.c +++ b/src/mesa/drivers/dri/radeon/radeon_state_init.c @@ -38,39 +38,156 @@ @@ -30975,7 +31930,7 @@ index 57dc380..7ff0eb4 100644 } -@@ -146,42 +263,290 @@ CHECK( txr0, (ctx->Texture.Unit[0]._ReallyEnabled & TEXTURE_RECT_BIT)) +@@ -146,81 +263,379 @@ CHECK( txr0, (ctx->Texture.Unit[0]._ReallyEnabled & TEXTURE_RECT_BIT)) CHECK( txr1, (ctx->Texture.Unit[1]._ReallyEnabled & TEXTURE_RECT_BIT)) CHECK( txr2, (ctx->Texture.Unit[2]._ReallyEnabled & TEXTURE_RECT_BIT)) @@ -31158,10 +32113,11 @@ index 57dc380..7ff0eb4 100644 + } + + /* output the first 7 bytes of context */ ++ dwords = 10; + if (drb) -+ dwords += 4; ++ dwords += 6; + if (rrb) -+ dwords += 4; ++ dwords += 6; + BEGIN_BATCH_NO_AUTOSTATE(dwords); + + /* In the CS case we need to split this up */ @@ -31170,7 +32126,7 @@ index 57dc380..7ff0eb4 100644 + + if (drb) { + OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHOFFSET, 0)); -+ OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); ++ OUT_BATCH_RELOC(0, drb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); + + OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHPITCH, 0)); + OUT_BATCH(zbpitch); @@ -31185,14 +32141,12 @@ index 57dc380..7ff0eb4 100644 + if (rrb) { + OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLOROFFSET, 0)); + OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); ++ ++ OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0)); ++ OUT_BATCH(cbpitch); } - rmesa->state.color.clear = 0x00000000; -+ if (rrb) { -+ OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0)); -+ OUT_BATCH(cbpitch); -+ } -+ + // if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM) { + // OUT_BATCH_TABLE((atom->cmd + 14), 4); + // } @@ -31240,27 +32194,80 @@ index 57dc380..7ff0eb4 100644 + if (t && t->mt && !t->image_override) + dwords += 2; + BEGIN_BATCH_NO_AUTOSTATE(dwords); ++ + OUT_BATCH_TABLE(atom->cmd, 3); + if (t && t->mt && !t->image_override) { + if ((ctx->Texture.Unit[i]._ReallyEnabled & TEXTURE_CUBE_BIT)) { + lvl = &t->mt->levels[0]; + OUT_BATCH_RELOC(lvl->faces[5].offset, t->mt->bo, lvl->faces[5].offset, -+ RADEON_GEM_DOMAIN_VRAM, 0, 0); ++ RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); + } else { + OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0, -+ RADEON_GEM_DOMAIN_VRAM, 0, 0); ++ RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); + } + } else if (!t) { + /* workaround for old CS mechanism */ + OUT_BATCH(r100->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]); + // OUT_BATCH(r100->radeon.radeonScreen); -+ } else if (t->image_override) ++ } else { + OUT_BATCH(t->override_offset); ++ } + + OUT_BATCH_TABLE((atom->cmd+4), 5); + END_BATCH(); +} + ++static void tex_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom) ++{ ++ r100ContextPtr r100 = R100_CONTEXT(ctx); ++ BATCH_LOCALS(&r100->radeon); ++ uint32_t dwords = atom->cmd_size; ++ int i = atom->idx; ++ radeonTexObj *t = r100->state.texture.unit[i].texobj; ++ radeon_mipmap_level *lvl; ++ int hastexture = 1; ++ ++ if (!t) ++ hastexture = 0; ++ else { ++ if (!t->mt && !t->bo) ++ hastexture = 0; ++ } ++ dwords += 1; ++ if (hastexture) ++ dwords += 2; ++ else ++ dwords -= 2; ++ BEGIN_BATCH_NO_AUTOSTATE(dwords); ++ ++ OUT_BATCH(CP_PACKET0(RADEON_PP_TXFILTER_0 + (24 * i), 1)); ++ OUT_BATCH_TABLE((atom->cmd + 1), 2); ++ ++ if (hastexture) { ++ OUT_BATCH(CP_PACKET0(RADEON_PP_TXOFFSET_0 + (24 * i), 0)); ++ if (t->mt && !t->image_override) { ++ if ((ctx->Texture.Unit[i]._ReallyEnabled & TEXTURE_CUBE_BIT)) { ++ lvl = &t->mt->levels[0]; ++ OUT_BATCH_RELOC(lvl->faces[5].offset, t->mt->bo, lvl->faces[5].offset, ++ RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); ++ } else { ++ OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0, ++ RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); ++ } ++ } else { ++ if (t->bo) ++ OUT_BATCH_RELOC(t->tile_bits, t->bo, 0, ++ RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); ++ } ++ } ++ ++ OUT_BATCH(CP_PACKET0(RADEON_PP_TXCBLEND_0 + (i * 24), 1)); ++ OUT_BATCH_TABLE((atom->cmd+4), 2); ++ OUT_BATCH(CP_PACKET0(RADEON_PP_BORDER_COLOR_0 + (i * 4), 0)); ++ OUT_BATCH((atom->cmd[TEX_PP_BORDER_COLOR])); ++ END_BATCH(); ++} ++ +/* Initialize the context's hardware state. + */ +void radeonInitState( r100ContextPtr rmesa ) @@ -31290,8 +32297,10 @@ index 57dc380..7ff0eb4 100644 + rmesa->radeon.state.stencil.clear = 0xffff0000; break; default: - fprintf( stderr, "Error: Unsupported depth %d... exiting\n", -@@ -190,37 +555,37 @@ void radeonInitState( radeonContextPtr rmesa ) +- fprintf( stderr, "Error: Unsupported depth %d... exiting\n", +- ctx->Visual.depthBits ); +- exit( -1 ); ++ break; } /* Only have hw stencil when depth buffer is 24 bits deep */ @@ -31347,7 +32356,7 @@ index 57dc380..7ff0eb4 100644 ALLOC_STATE( lin, always, LIN_STATE_SIZE, "LIN/line", 0 ); ALLOC_STATE( msk, always, MSK_STATE_SIZE, "MSK/mask", 0 ); ALLOC_STATE( vpt, always, VPT_STATE_SIZE, "VPT/viewport", 0 ); -@@ -233,20 +598,25 @@ void radeonInitState( radeonContextPtr rmesa ) +@@ -233,20 +648,29 @@ void radeonInitState( radeonContextPtr rmesa ) ALLOC_STATE( fog, fog, FOG_STATE_SIZE, "FOG/fog", 1 ); ALLOC_STATE( glt, tcl_lighting, GLT_STATE_SIZE, "GLT/light-global", 1 ); ALLOC_STATE( eye, tcl_lighting, EYE_STATE_SIZE, "EYE/eye-vector", 1 ); @@ -31357,10 +32366,14 @@ index 57dc380..7ff0eb4 100644 - if (rmesa->radeonScreen->drmSupportsCubeMapsR100) + ALLOC_STATE_IDX( tex[0], tex0, TEX_STATE_SIZE, "TEX/tex-0", 0, 0); + ALLOC_STATE_IDX( tex[1], tex1, TEX_STATE_SIZE, "TEX/tex-1", 0, 1); -+ ALLOC_STATE_IDX( tex[2], tex2, TEX_STATE_SIZE, "TEX/tex-2", 0, 2 ); ++ ALLOC_STATE_IDX( tex[2], tex2, TEX_STATE_SIZE, "TEX/tex-2", 0, 2); + -+ for (i = 0; i < 3; i++) -+ rmesa->hw.tex[i].emit = tex_emit; ++ for (i = 0; i < 3; i++) { ++ if (rmesa->radeon.radeonScreen->kernel_mm) ++ rmesa->hw.tex[i].emit = tex_emit_cs; ++ else ++ rmesa->hw.tex[i].emit = tex_emit; ++ } + if (rmesa->radeon.radeonScreen->drmSupportsCubeMapsR100) { - ALLOC_STATE( cube[0], cube0, CUBE_STATE_SIZE, "CUBE/cube-0", 0 ); @@ -31383,7 +32396,7 @@ index 57dc380..7ff0eb4 100644 } ALLOC_STATE( mat[0], tcl, MAT_STATE_SIZE, "MAT/modelproject", 1 ); ALLOC_STATE( mat[1], tcl_eyespace_or_fog, MAT_STATE_SIZE, "MAT/modelview", 1 ); -@@ -268,43 +638,43 @@ void radeonInitState( radeonContextPtr rmesa ) +@@ -268,43 +692,43 @@ void radeonInitState( radeonContextPtr rmesa ) ALLOC_STATE( lit[5], tcl_lit5, LIT_STATE_SIZE, "LIT/light-5", 1 ); ALLOC_STATE( lit[6], tcl_lit6, LIT_STATE_SIZE, "LIT/light-6", 1 ); ALLOC_STATE( lit[7], tcl_lit7, LIT_STATE_SIZE, "LIT/light-7", 1 ); @@ -31458,7 +32471,7 @@ index 57dc380..7ff0eb4 100644 rmesa->hw.grd.cmd[GRD_CMD_0] = cmdscl( RADEON_SS_VERT_GUARD_CLIP_ADJ_ADDR, 1, 4 ); rmesa->hw.fog.cmd[FOG_CMD_0] = -@@ -331,6 +701,22 @@ void radeonInitState( radeonContextPtr rmesa ) +@@ -331,6 +755,22 @@ void radeonInitState( radeonContextPtr rmesa ) cmdvec( RADEON_VS_UCP_ADDR + i, 1, 4 ); } @@ -31481,7 +32494,7 @@ index 57dc380..7ff0eb4 100644 rmesa->last_ReallyEnabled = -1; /* Initial Harware state: -@@ -352,19 +738,7 @@ void radeonInitState( radeonContextPtr rmesa ) +@@ -352,19 +792,7 @@ void radeonInitState( radeonContextPtr rmesa ) RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ZERO ); @@ -31502,7 +32515,7 @@ index 57dc380..7ff0eb4 100644 RADEON_STENCIL_TEST_ALWAYS | RADEON_STENCIL_FAIL_KEEP | RADEON_STENCIL_ZPASS_KEEP | -@@ -374,7 +748,7 @@ void radeonInitState( radeonContextPtr rmesa ) +@@ -374,7 +802,7 @@ void radeonInitState( radeonContextPtr rmesa ) if (rmesa->using_hyperz) { rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_COMPRESSION_ENABLE | RADEON_Z_DECOMPRESSION_ENABLE; @@ -31511,7 +32524,7 @@ index 57dc380..7ff0eb4 100644 /* works for q3, but slight rendering errors with glxgears ? */ /* rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_HIERARCHY_ENABLE;*/ /* need this otherwise get lots of lockups with q3 ??? */ -@@ -386,10 +760,9 @@ void radeonInitState( radeonContextPtr rmesa ) +@@ -386,10 +814,9 @@ void radeonInitState( radeonContextPtr rmesa ) RADEON_ANTI_ALIAS_NONE); rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = (RADEON_PLANE_MASK_ENABLE | @@ -31523,7 +32536,7 @@ index 57dc380..7ff0eb4 100644 case DRI_CONF_DITHER_XERRORDIFFRESET: rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_INIT; break; -@@ -397,30 +770,17 @@ void radeonInitState( radeonContextPtr rmesa ) +@@ -397,30 +824,17 @@ void radeonInitState( radeonContextPtr rmesa ) rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_SCALE_DITHER_ENABLE; break; } @@ -31559,7 +32572,7 @@ index 57dc380..7ff0eb4 100644 rmesa->hw.set.cmd[SET_SE_CNTL] = (RADEON_FFACE_CULL_CCW | RADEON_BFACE_SOLID | -@@ -444,7 +804,7 @@ void radeonInitState( radeonContextPtr rmesa ) +@@ -444,7 +858,7 @@ void radeonInitState( radeonContextPtr rmesa ) RADEON_VC_NO_SWAP; #endif @@ -31568,7 +32581,7 @@ index 57dc380..7ff0eb4 100644 rmesa->hw.set.cmd[SET_SE_CNTL_STATUS] |= RADEON_TCL_BYPASS; } -@@ -491,8 +851,8 @@ void radeonInitState( radeonContextPtr rmesa ) +@@ -491,8 +905,8 @@ void radeonInitState( radeonContextPtr rmesa ) (2 << RADEON_TXFORMAT_HEIGHT_SHIFT)); /* Initialize the texture offset to the start of the card texture heap */ @@ -31579,7 +32592,7 @@ index 57dc380..7ff0eb4 100644 rmesa->hw.tex[i].cmd[TEX_PP_BORDER_COLOR] = 0; rmesa->hw.tex[i].cmd[TEX_PP_TXCBLEND] = -@@ -513,15 +873,15 @@ void radeonInitState( radeonContextPtr rmesa ) +@@ -513,15 +927,15 @@ void radeonInitState( radeonContextPtr rmesa ) rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_FACES] = 0; rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_0] = @@ -31600,7 +32613,7 @@ index 57dc380..7ff0eb4 100644 } /* Can only add ST1 at the time of doing some multitex but can keep -@@ -613,5 +973,7 @@ void radeonInitState( radeonContextPtr rmesa ) +@@ -613,5 +1027,7 @@ void radeonInitState( radeonContextPtr rmesa ) rmesa->hw.eye.cmd[EYE_Z] = IEEE_ONE; rmesa->hw.eye.cmd[EYE_RESCALE_FACTOR] = IEEE_ONE; @@ -32908,11 +33921,14 @@ index b0aec21..2dfb504 100644 driInitTextureFormats(); } diff --git a/src/mesa/drivers/dri/radeon/radeon_tex.h b/src/mesa/drivers/dri/radeon/radeon_tex.h -index 8000880..8c2f9be 100644 +index 8000880..4c2fba4 100644 --- a/src/mesa/drivers/dri/radeon/radeon_tex.h +++ b/src/mesa/drivers/dri/radeon/radeon_tex.h -@@ -43,10 +43,10 @@ extern void radeonSetTexOffset(__DRIcontext *pDRICtx, GLint texname, +@@ -41,12 +41,13 @@ extern void radeonSetTexOffset(__DRIcontext *pDRICtx, GLint texname, + unsigned long long offset, GLint depth, + GLuint pitch); ++extern void radeonSetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv); extern void radeonUpdateTextureState( GLcontext *ctx ); -extern int radeonUploadTexImages( radeonContextPtr rmesa, radeonTexObjPtr t, @@ -33335,10 +34351,15 @@ index 5f7bbe6..0000000 - return 0; -} diff --git a/src/mesa/drivers/dri/radeon/radeon_texstate.c b/src/mesa/drivers/dri/radeon/radeon_texstate.c -index 1e2f654..6a34f1e 100644 +index 1e2f654..06771a3 100644 --- a/src/mesa/drivers/dri/radeon/radeon_texstate.c +++ b/src/mesa/drivers/dri/radeon/radeon_texstate.c -@@ -43,6 +43,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +@@ -39,10 +39,12 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + #include "main/context.h" + #include "main/macros.h" + #include "main/texformat.h" ++#include "main/teximage.h" + #include "main/texobj.h" #include "main/enums.h" #include "radeon_context.h" @@ -33346,7 +34367,7 @@ index 1e2f654..6a34f1e 100644 #include "radeon_state.h" #include "radeon_ioctl.h" #include "radeon_swtcl.h" -@@ -75,10 +76,11 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +@@ -75,10 +77,11 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define VALID_FORMAT(f) ( ((f) <= MESA_FORMAT_RGBA_DXT5) \ && (tx_table[f].format != 0xffffffff) ) @@ -33361,7 +34382,7 @@ index 1e2f654..6a34f1e 100644 { _ALPHA(RGBA8888), _ALPHA_REV(RGBA8888), -@@ -111,252 +113,6 @@ tx_table[] = +@@ -111,252 +114,6 @@ tx_table[] = #undef _ALPHA #undef _INVALID @@ -33614,7 +34635,7 @@ index 1e2f654..6a34f1e 100644 /* ================================================================ * Texture combine functions */ -@@ -503,7 +259,7 @@ do { \ +@@ -503,7 +260,7 @@ do { \ static GLboolean radeonUpdateTextureEnv( GLcontext *ctx, int unit ) { @@ -33623,7 +34644,7 @@ index 1e2f654..6a34f1e 100644 const struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit]; GLuint color_combine, alpha_combine; const GLuint color_combine0 = RADEON_COLOR_ARG_A_ZERO | RADEON_COLOR_ARG_B_ZERO -@@ -846,22 +602,21 @@ static GLboolean radeonUpdateTextureEnv( GLcontext *ctx, int unit ) +@@ -846,22 +603,21 @@ static GLboolean radeonUpdateTextureEnv( GLcontext *ctx, int unit ) void radeonSetTexOffset(__DRIcontext * pDRICtx, GLint texname, unsigned long long offset, GLint depth, GLuint pitch) { @@ -33652,7 +34673,117 @@ index 1e2f654..6a34f1e 100644 t->pp_txpitch = pitch - 32; switch (depth) { -@@ -901,12 +656,58 @@ void radeonSetTexOffset(__DRIcontext * pDRICtx, GLint texname, +@@ -881,6 +637,109 @@ void radeonSetTexOffset(__DRIcontext * pDRICtx, GLint texname, + } + } + ++void radeonSetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv) ++{ ++ struct gl_texture_unit *texUnit; ++ struct gl_texture_object *texObj; ++ struct gl_texture_image *texImage; ++ struct radeon_renderbuffer *rb; ++ radeon_texture_image *rImage; ++ radeonContextPtr radeon; ++ r100ContextPtr rmesa; ++ struct radeon_framebuffer *rfb; ++ radeonTexObjPtr t; ++ uint32_t pitch_val; ++ ++ target = GL_TEXTURE_RECTANGLE_ARB; ++ ++ radeon = pDRICtx->driverPrivate; ++ rmesa = pDRICtx->driverPrivate; ++ ++ rfb = dPriv->driverPrivate; ++ texUnit = &radeon->glCtx->Texture.Unit[radeon->glCtx->Texture.CurrentUnit]; ++ texObj = _mesa_select_tex_object(radeon->glCtx, texUnit, target); ++ texImage = _mesa_get_tex_image(radeon->glCtx, texObj, target, 0); ++ ++ rImage = get_radeon_texture_image(texImage); ++ t = radeon_tex_obj(texObj); ++ if (t == NULL) { ++ return; ++ } ++ ++ radeon_update_renderbuffers(pDRICtx, dPriv); ++ /* back & depth buffer are useless free them right away */ ++ rb = (void*)rfb->base.Attachment[BUFFER_DEPTH].Renderbuffer; ++ if (rb && rb->bo) { ++ radeon_bo_unref(rb->bo); ++ rb->bo = NULL; ++ } ++ rb = (void*)rfb->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer; ++ if (rb && rb->bo) { ++ radeon_bo_unref(rb->bo); ++ rb->bo = NULL; ++ } ++ rb = (void*)rfb->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer; ++ if (rb->bo == NULL) { ++ /* Failed to BO for the buffer */ ++ return; ++ } ++ ++ _mesa_lock_texture(radeon->glCtx, texObj); ++ if (t->bo) { ++ radeon_bo_unref(t->bo); ++ t->bo = NULL; ++ } ++ if (rImage->bo) { ++ radeon_bo_unref(rImage->bo); ++ rImage->bo = NULL; ++ } ++ if (t->mt) { ++ radeon_miptree_unreference(t->mt); ++ t->mt = NULL; ++ } ++ if (rImage->mt) { ++ radeon_miptree_unreference(rImage->mt); ++ rImage->mt = NULL; ++ } ++ fprintf(stderr,"settexbuf %d %dx%d@%d\n", rb->pitch, rb->width, rb->height, rb->cpp); ++ _mesa_init_teximage_fields(radeon->glCtx, target, texImage, ++ rb->width, rb->height, 1, 0, rb->cpp); ++ texImage->TexFormat = &_mesa_texformat_rgba8888_rev; ++ rImage->bo = rb->bo; ++ radeon_bo_ref(rImage->bo); ++ t->bo = rb->bo; ++ radeon_bo_ref(t->bo); ++ t->tile_bits = 0; ++ t->image_override = GL_TRUE; ++ t->override_offset = 0; ++ t->pp_txpitch &= (1 << 13) -1; ++ pitch_val = rb->pitch; ++ switch (rb->cpp) { ++ case 4: ++ t->pp_txformat = tx_table[MESA_FORMAT_ARGB8888].format; ++ t->pp_txfilter |= tx_table[MESA_FORMAT_ARGB8888].filter; ++ break; ++ case 3: ++ default: ++ t->pp_txformat = tx_table[MESA_FORMAT_RGB888].format; ++ t->pp_txfilter |= tx_table[MESA_FORMAT_RGB888].filter; ++ break; ++ case 2: ++ t->pp_txformat = tx_table[MESA_FORMAT_RGB565].format; ++ t->pp_txfilter |= tx_table[MESA_FORMAT_RGB565].filter; ++ break; ++ } ++ t->pp_txsize = ((rb->width - 1) << RADEON_TEX_USIZE_SHIFT) ++ | ((rb->height - 1) << RADEON_TEX_VSIZE_SHIFT); ++ t->pp_txformat |= RADEON_TXFORMAT_NON_POWER2; ++ t->pp_txpitch = pitch_val; ++ t->pp_txpitch -= 32; ++ ++ t->validated = GL_TRUE; ++ _mesa_unlock_texture(radeon->glCtx, texObj); ++ return; ++} ++ + #define TEXOBJ_TXFILTER_MASK (RADEON_MAX_MIP_LEVEL_MASK | \ + RADEON_MIN_FILTER_MASK | \ + RADEON_MAG_FILTER_MASK | \ +@@ -901,12 +760,58 @@ void radeonSetTexOffset(__DRIcontext * pDRICtx, GLint texname, RADEON_TXFORMAT_NON_POWER2) @@ -33713,7 +34844,7 @@ index 1e2f654..6a34f1e 100644 GLuint se_coord_fmt = rmesa->hw.set.cmd[SET_SE_COORDFMT]; RADEON_STATECHANGE( rmesa, tex[unit] ); -@@ -915,10 +716,9 @@ static void import_tex_obj_state( radeonContextPtr rmesa, +@@ -915,10 +820,9 @@ static void import_tex_obj_state( radeonContextPtr rmesa, cmd[TEX_PP_TXFILTER] |= texobj->pp_txfilter & TEXOBJ_TXFILTER_MASK; cmd[TEX_PP_TXFORMAT] &= ~TEXOBJ_TXFORMAT_MASK; cmd[TEX_PP_TXFORMAT] |= texobj->pp_txformat & TEXOBJ_TXFORMAT_MASK; @@ -33725,7 +34856,7 @@ index 1e2f654..6a34f1e 100644 GLuint *txr_cmd = RADEON_DB_STATE( txr[unit] ); txr_cmd[TXR_PP_TEX_SIZE] = texobj->pp_txsize; /* NPOT only! */ txr_cmd[TXR_PP_TEX_PITCH] = texobj->pp_txpitch; /* NPOT only! */ -@@ -928,22 +728,12 @@ static void import_tex_obj_state( radeonContextPtr rmesa, +@@ -928,22 +832,12 @@ static void import_tex_obj_state( radeonContextPtr rmesa, else { se_coord_fmt &= ~(RADEON_VTX_ST0_NONPARAMETRIC << unit); @@ -33751,7 +34882,7 @@ index 1e2f654..6a34f1e 100644 } } -@@ -952,13 +742,11 @@ static void import_tex_obj_state( radeonContextPtr rmesa, +@@ -952,13 +846,11 @@ static void import_tex_obj_state( radeonContextPtr rmesa, rmesa->hw.set.cmd[SET_SE_COORDFMT] = se_coord_fmt; } @@ -33767,7 +34898,7 @@ index 1e2f654..6a34f1e 100644 GLuint unit, const GLfloat *s_plane, const GLfloat *t_plane, -@@ -986,14 +774,14 @@ static void set_texgen_matrix( radeonContextPtr rmesa, +@@ -986,14 +878,14 @@ static void set_texgen_matrix( radeonContextPtr rmesa, rmesa->TexGenMatrix[unit].m[15] = q_plane[3]; rmesa->TexGenEnabled |= RADEON_TEXMAT_0_ENABLE << unit; @@ -33784,7 +34915,7 @@ index 1e2f654..6a34f1e 100644 struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit]; GLuint inputshift = RADEON_TEXGEN_0_INPUT_SHIFT + unit*4; GLuint tmp = rmesa->TexGenEnabled; -@@ -1094,283 +882,185 @@ static GLboolean radeon_validate_texgen( GLcontext *ctx, GLuint unit ) +@@ -1094,283 +986,189 @@ static GLboolean radeon_validate_texgen( GLcontext *ctx, GLuint unit ) } if (tmp != rmesa->TexGenEnabled) { @@ -33893,16 +35024,18 @@ index 1e2f654..6a34f1e 100644 - struct gl_texture_object *tObj = texUnit->_Current; - radeonTexObjPtr t = (radeonTexObjPtr) tObj->DriverData; - GLuint face; -- ++ const struct gl_texture_image *firstImage; ++ GLint log2Width, log2Height, log2Depth, texelBytes; + - /* Need to load the 2d images associated with this unit. - */ - if (t->pp_txformat & RADEON_TXFORMAT_NON_POWER2) { - t->pp_txformat &= ~RADEON_TXFORMAT_NON_POWER2; - for (face = 0; face < 6; face++) - t->base.dirty_images[face] = ~0; -- } -+ const struct gl_texture_image *firstImage; -+ GLint log2Width, log2Height, log2Depth, texelBytes; ++ if ( t->bo ) { ++ return GL_TRUE; + } - ASSERT(tObj->Target == GL_TEXTURE_CUBE_MAP); + firstImage = t->base.Image[0][t->mt->firstLevel]; @@ -33980,16 +35113,16 @@ index 1e2f654..6a34f1e 100644 - return GL_TRUE; -} -+ t->pp_txsize = (((firstImage->Width - 1) << RADEON_TEX_USIZE_SHIFT) -+ | ((firstImage->Height - 1) << RADEON_TEX_VSIZE_SHIFT)); - +- -static GLboolean enable_tex_rect( GLcontext *ctx, int unit ) -{ - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); - struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit]; - struct gl_texture_object *tObj = texUnit->_Current; - radeonTexObjPtr t = (radeonTexObjPtr) tObj->DriverData; -- ++ t->pp_txsize = (((firstImage->Width - 1) << RADEON_TEX_USIZE_SHIFT) ++ | ((firstImage->Height - 1) << RADEON_TEX_VSIZE_SHIFT)); + - if (!(t->pp_txformat & RADEON_TXFORMAT_NON_POWER2)) { - t->pp_txformat |= RADEON_TXFORMAT_NON_POWER2; - t->base.dirty_images[0] = ~0; @@ -34059,27 +35192,27 @@ index 1e2f654..6a34f1e 100644 - rmesa->state.texture.unit[unit].texobj->base.bound &= - ~(1UL << unit); - } -+ RADEON_STATECHANGE( rmesa, ctx ); -+ rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= -+ (RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE) << unit; - +- - rmesa->state.texture.unit[unit].texobj = t; - t->base.bound |= (1UL << unit); - t->dirty_state |= 1<hw.ctx.cmd[CTX_PP_CNTL] |= ++ (RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE) << unit; + + RADEON_STATECHANGE( rmesa, tcl ); + rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] |= RADEON_ST_BIT(unit); -+ rmesa->recheck_texgen[unit] = GL_TRUE; - - /* Newly enabled? - */ - if ( !(rmesa->hw.ctx.cmd[CTX_PP_CNTL] & (RADEON_TEX_0_ENABLE<hw.ctx.cmd[CTX_PP_CNTL] |= - (RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE) << unit; -- ++ rmesa->recheck_texgen[unit] = GL_TRUE; + - RADEON_STATECHANGE( rmesa, tcl ); - - rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] |= RADEON_ST_BIT(unit);