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add patch to disable NEON on aarch64 for vc4 driver (fixes FTBFS)
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2 changed files with 42 additions and 0 deletions
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@ -78,6 +78,7 @@ Patch1: 0001-llvm-SONAME-without-version.patch
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Patch2: 0002-hardware-gloat.patch
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Patch3: 0003-evergreen-big-endian.patch
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Patch4: 0004-bigendian-assert.patch
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Patch5: vc4-Only-build-the-NEON-code-on-arm32.patch
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# glvnd support patches
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# non-upstreamed ones
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41
vc4-Only-build-the-NEON-code-on-arm32.patch
Normal file
41
vc4-Only-build-the-NEON-code-on-arm32.patch
Normal file
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@ -0,0 +1,41 @@
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From patchwork Fri Apr 14 17:47:45 2017
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Content-Type: text/plain; charset="utf-8"
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MIME-Version: 1.0
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Content-Transfer-Encoding: 7bit
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Subject: [Mesa-dev,v3,4/4] vc4: Only build the NEON code on arm32.
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From: Eric Anholt <eric@anholt.net>
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X-Patchwork-Id: 150580
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Message-Id: <20170414174745.14223-4-eric@anholt.net>
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To: mesa-dev@lists.freedesktop.org
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Date: Fri, 14 Apr 2017 10:47:45 -0700
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NEON is sufficiently different on arm64 that we can't just reuse this
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code. Disable it on arm64 for now.
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Signed-off-by: Eric Anholt <eric@anholt.net>
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---
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src/gallium/drivers/vc4/vc4_tiling_lt.c | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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diff --git a/src/gallium/drivers/vc4/vc4_tiling_lt.c b/src/gallium/drivers/vc4/vc4_tiling_lt.c
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index c9cbc65e2dbc..7de67b652daa 100644
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--- a/src/gallium/drivers/vc4/vc4_tiling_lt.c
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+++ b/src/gallium/drivers/vc4/vc4_tiling_lt.c
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@@ -61,7 +61,7 @@ static void
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vc4_load_utile(void *cpu, void *gpu, uint32_t cpu_stride, uint32_t cpp)
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{
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uint32_t gpu_stride = vc4_utile_stride(cpp);
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-#if defined(VC4_BUILD_NEON) && defined(__ARM_ARCH)
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+#if defined(VC4_BUILD_NEON) && defined(__ARM_ARCH) && __ARM_ARCH <= 7
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if (gpu_stride == 8) {
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__asm__ volatile (
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/* Load from the GPU in one shot, no interleave, to
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@@ -118,7 +118,7 @@ vc4_store_utile(void *gpu, void *cpu, uint32_t cpu_stride, uint32_t cpp)
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{
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uint32_t gpu_stride = vc4_utile_stride(cpp);
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-#if defined(VC4_BUILD_NEON) && defined(__ARM_ARCH)
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+#if defined(VC4_BUILD_NEON) && defined(__ARM_ARCH) && __ARM_ARCH <= 7
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if (gpu_stride == 8) {
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__asm__ volatile (
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/* Load each 8-byte line from cpu-side source,
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