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Revert upstream patches causing SNB regression.
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2 changed files with 131 additions and 1 deletions
125
mesa-intel-snb-regression-reverts.patch
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125
mesa-intel-snb-regression-reverts.patch
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@ -0,0 +1,125 @@
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diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c
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index 32ee37f..21ce92c 100644
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--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
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+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
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@@ -52,35 +52,6 @@ static void guess_execution_size(struct brw_compile *p,
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}
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-/**
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- * Prior to Sandybridge, the SEND instruction accepted non-MRF source
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- * registers, implicitly moving the operand to a message register.
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- *
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- * On Sandybridge, this is no longer the case. This function performs the
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- * explicit move; it should be called before emitting a SEND instruction.
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- */
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-static void
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-gen6_resolve_implied_move(struct brw_compile *p,
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- struct brw_reg *src,
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- GLuint msg_reg_nr)
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-{
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- struct intel_context *intel = &p->brw->intel;
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- if (intel->gen != 6)
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- return;
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-
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- if (src->file == BRW_ARCHITECTURE_REGISTER_FILE && src->nr == BRW_ARF_NULL)
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- return;
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-
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- brw_push_insn_state(p);
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- brw_set_mask_control(p, BRW_MASK_DISABLE);
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- brw_set_compression_control(p, BRW_COMPRESSION_NONE);
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- brw_MOV(p, retype(brw_message_reg(msg_reg_nr), BRW_REGISTER_TYPE_UD),
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- retype(*src, BRW_REGISTER_TYPE_UD));
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- brw_pop_insn_state(p);
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- *src = brw_message_reg(msg_reg_nr);
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-}
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-
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-
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static void brw_set_dest(struct brw_compile *p,
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struct brw_instruction *insn,
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struct brw_reg dest)
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@@ -1800,7 +1771,6 @@ void brw_dp_READ_4_vs_relative(struct brw_compile *p,
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GLuint bind_table_index)
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{
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struct intel_context *intel = &p->brw->intel;
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- struct brw_reg src = brw_vec8_grf(0, 0);
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int msg_type;
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/* Setup MRF[1] with offset into const buffer */
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@@ -1817,7 +1787,6 @@ void brw_dp_READ_4_vs_relative(struct brw_compile *p,
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addr_reg, brw_imm_d(offset));
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brw_pop_insn_state(p);
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- gen6_resolve_implied_move(p, &src, 0);
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struct brw_instruction *insn = next_insn(p, BRW_OPCODE_SEND);
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insn->header.predicate_control = BRW_PREDICATE_NONE;
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@@ -1826,7 +1795,7 @@ void brw_dp_READ_4_vs_relative(struct brw_compile *p,
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insn->header.mask_control = BRW_MASK_DISABLE;
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brw_set_dest(p, insn, dest);
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- brw_set_src0(insn, src);
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+ brw_set_src0(insn, brw_vec8_grf(0, 0));
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if (intel->gen == 6)
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msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
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@@ -1997,7 +1966,20 @@ void brw_SAMPLE(struct brw_compile *p,
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{
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struct brw_instruction *insn;
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- gen6_resolve_implied_move(p, &src0, msg_reg_nr);
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+ /* Sandybridge doesn't have the implied move for SENDs,
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+ * and the first message register index comes from src0.
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+ */
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+ if (intel->gen >= 6) {
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+ if (src0.file != BRW_ARCHITECTURE_REGISTER_FILE ||
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+ src0.nr != BRW_ARF_NULL) {
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+ brw_push_insn_state(p);
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+ brw_set_mask_control( p, BRW_MASK_DISABLE );
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+ brw_set_compression_control(p, BRW_COMPRESSION_NONE);
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+ brw_MOV(p, retype(brw_message_reg(msg_reg_nr), src0.type), src0);
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+ brw_pop_insn_state(p);
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+ }
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+ src0 = brw_message_reg(msg_reg_nr);
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+ }
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insn = next_insn(p, BRW_OPCODE_SEND);
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insn->header.predicate_control = 0; /* XXX */
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@@ -2052,7 +2034,17 @@ void brw_urb_WRITE(struct brw_compile *p,
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struct intel_context *intel = &p->brw->intel;
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struct brw_instruction *insn;
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- gen6_resolve_implied_move(p, &src0, msg_reg_nr);
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+ /* Sandybridge doesn't have the implied move for SENDs,
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+ * and the first message register index comes from src0.
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+ */
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+ if (intel->gen >= 6) {
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+ brw_push_insn_state(p);
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+ brw_set_mask_control( p, BRW_MASK_DISABLE );
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+ brw_MOV(p, retype(brw_message_reg(msg_reg_nr), BRW_REGISTER_TYPE_UD),
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+ retype(src0, BRW_REGISTER_TYPE_UD));
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+ brw_pop_insn_state(p);
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+ src0 = brw_message_reg(msg_reg_nr);
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+ }
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insn = next_insn(p, BRW_OPCODE_SEND);
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@@ -2162,7 +2154,17 @@ void brw_ff_sync(struct brw_compile *p,
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struct intel_context *intel = &p->brw->intel;
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struct brw_instruction *insn;
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- gen6_resolve_implied_move(p, &src0, msg_reg_nr);
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+ /* Sandybridge doesn't have the implied move for SENDs,
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+ * and the first message register index comes from src0.
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+ */
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+ if (intel->gen >= 6) {
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+ brw_push_insn_state(p);
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+ brw_set_mask_control( p, BRW_MASK_DISABLE );
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+ brw_MOV(p, retype(brw_message_reg(msg_reg_nr), BRW_REGISTER_TYPE_UD),
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+ retype(src0, BRW_REGISTER_TYPE_UD));
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+ brw_pop_insn_state(p);
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+ src0 = brw_message_reg(msg_reg_nr);
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+ }
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insn = next_insn(p, BRW_OPCODE_SEND);
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brw_set_dest(p, insn, dest);
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@ -18,7 +18,7 @@
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Summary: Mesa graphics libraries
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Summary: Mesa graphics libraries
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Name: mesa
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Name: mesa
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Version: 7.11
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Version: 7.11
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Release: 0.4.%{gitdate}.0%{?dist}
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Release: 0.5.%{gitdate}.0%{?dist}
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License: MIT
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License: MIT
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Group: System Environment/Libraries
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Group: System Environment/Libraries
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URL: http://www.mesa3d.org
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URL: http://www.mesa3d.org
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@ -31,6 +31,7 @@ Source2: %{manpages}.tar.bz2
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Source3: make-git-snapshot.sh
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Source3: make-git-snapshot.sh
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Source4: llvmcore.mk
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Source4: llvmcore.mk
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Patch1: mesa-intel-snb-regression-reverts.patch
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Patch2: mesa-7.1-nukeglthread-debug.patch
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Patch2: mesa-7.1-nukeglthread-debug.patch
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Patch3: mesa-no-mach64.patch
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Patch3: mesa-no-mach64.patch
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Patch4: legacy-drivers.patch
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Patch4: legacy-drivers.patch
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@ -214,6 +215,7 @@ Requires: Xorg %(xserver-sdk-abi-requires ansic) %(xserver-sdk-abi-requires vide
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%prep
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%prep
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#setup -q -n Mesa-%{version}%{?snapshot} -b0 -b2
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#setup -q -n Mesa-%{version}%{?snapshot} -b0 -b2
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%setup -q -n mesa-%{gitdate} -b2
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%setup -q -n mesa-%{gitdate} -b2
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%patch1 -p1 -b .intel-fix
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%patch2 -p1 -b .intel-glthread
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%patch2 -p1 -b .intel-glthread
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%patch3 -p1 -b .no-mach64
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%patch3 -p1 -b .no-mach64
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%patch4 -p1 -b .classic
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%patch4 -p1 -b .classic
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@ -485,6 +487,9 @@ rm -rf $RPM_BUILD_ROOT
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%{_libdir}/libOSMesa.so
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%{_libdir}/libOSMesa.so
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%changelog
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%changelog
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* Fri Apr 01 2011 Dave Airlie <airlied@redhat.com> 7.11-0.5.20110401.0
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- Revert upstream patches causing SNB regression.
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* Fri Apr 01 2011 Dave Airlie <airlied@redhat.com> 7.11-0.4.20110401.0
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* Fri Apr 01 2011 Dave Airlie <airlied@redhat.com> 7.11-0.4.20110401.0
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- upstream snapshot again - proper fix for ILK + nv50 gnome-shell issue
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- upstream snapshot again - proper fix for ILK + nv50 gnome-shell issue
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