From 0d6d0340c0f1248bc666feb95fdfc6a5d4ab495c Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 24 Mar 2009 05:22:18 +0000 Subject: [PATCH] - radeon-rewrite: add FBO support for radeon on KMS/DRI2 --- radeon-rewrite.patch | 3460 ++++++++++++++++++++++++++---------------- 1 file changed, 2137 insertions(+), 1323 deletions(-) diff --git a/radeon-rewrite.patch b/radeon-rewrite.patch index 748faba..57bee5e 100644 --- a/radeon-rewrite.patch +++ b/radeon-rewrite.patch @@ -735,7 +735,7 @@ index e163377..ae31bcb 100644 - cmd[0].wait.flags = flags; -} diff --git a/src/mesa/drivers/dri/r200/r200_context.c b/src/mesa/drivers/dri/r200/r200_context.c -index c067515..10a6362 100644 +index c067515..d3898d0 100644 --- a/src/mesa/drivers/dri/r200/r200_context.c +++ b/src/mesa/drivers/dri/r200/r200_context.c @@ -54,7 +54,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. @@ -755,7 +755,15 @@ index c067515..10a6362 100644 #define need_GL_ARB_vertex_program #define need_GL_ATI_fragment_shader #define need_GL_EXT_blend_minmax -@@ -78,9 +79,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +@@ -71,6 +72,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + #define need_GL_EXT_blend_func_separate + #define need_GL_NV_vertex_program + #define need_GL_ARB_point_parameters ++#define need_GL_EXT_framebuffer_object + #include "extension_helper.h" + + #define DRIVER_DATE "20060602" +@@ -78,9 +80,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "vblank.h" #include "utils.h" #include "xmlpool.h" /* for symbolic values of enum-type options */ @@ -765,7 +773,7 @@ index c067515..10a6362 100644 /* Return various strings for glGetString(). */ -@@ -89,8 +87,8 @@ static const GLubyte *r200GetString( GLcontext *ctx, GLenum name ) +@@ -89,8 +88,8 @@ static const GLubyte *r200GetString( GLcontext *ctx, GLenum name ) r200ContextPtr rmesa = R200_CONTEXT(ctx); static char buffer[128]; unsigned offset; @@ -776,7 +784,7 @@ index c067515..10a6362 100644 switch ( name ) { case GL_VENDOR: -@@ -101,7 +99,7 @@ static const GLubyte *r200GetString( GLcontext *ctx, GLenum name ) +@@ -101,7 +100,7 @@ static const GLubyte *r200GetString( GLcontext *ctx, GLenum name ) agp_mode ); sprintf( & buffer[ offset ], " %sTCL", @@ -785,7 +793,27 @@ index c067515..10a6362 100644 ? "" : "NO-" ); return (GLubyte *)buffer; -@@ -234,6 +232,40 @@ static const struct dri_debug_control debug_control[] = +@@ -126,6 +125,7 @@ const struct dri_extension card_extensions[] = + { "GL_EXT_blend_minmax", GL_EXT_blend_minmax_functions }, + { "GL_EXT_blend_subtract", NULL }, + { "GL_EXT_fog_coord", GL_EXT_fog_coord_functions }, ++ { "GL_EXT_packed_depth_stencil", NULL}, + { "GL_EXT_secondary_color", GL_EXT_secondary_color_functions }, + { "GL_EXT_stencil_wrap", NULL }, + { "GL_EXT_texture_edge_clamp", NULL }, +@@ -167,6 +167,11 @@ const struct dri_extension point_extensions[] = { + { NULL, NULL } + }; + ++const struct dri_extension mm_extensions[] = { ++ { "GL_EXT_framebuffer_object", GL_EXT_framebuffer_object_functions }, ++ { NULL, NULL } ++}; ++ + extern const struct tnl_pipeline_stage _r200_render_stage; + extern const struct tnl_pipeline_stage _r200_tcl_stage; + +@@ -234,6 +239,40 @@ static const struct dri_debug_control debug_control[] = { NULL, 0 } }; @@ -826,7 +854,7 @@ index c067515..10a6362 100644 /* Create the device specific rendering context. */ -@@ -245,9 +277,9 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual, +@@ -245,9 +284,9 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual, radeonScreenPtr screen = (radeonScreenPtr)(sPriv->private); struct dd_function_table functions; r200ContextPtr rmesa; @@ -838,7 +866,7 @@ index c067515..10a6362 100644 assert(glVisual); assert(driContextPriv); -@@ -257,7 +289,8 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual, +@@ -257,7 +296,8 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual, rmesa = (r200ContextPtr) CALLOC( sizeof(*rmesa) ); if ( !rmesa ) return GL_FALSE; @@ -848,7 +876,7 @@ index c067515..10a6362 100644 /* init exp fog table data */ r200InitStaticFogData(); -@@ -265,12 +298,12 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual, +@@ -265,12 +305,12 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual, * Do this here so that initialMaxAnisotropy is set before we create * the default textures. */ @@ -865,7 +893,7 @@ index c067515..10a6362 100644 if ( sPriv->drm_version.minor < 13 ) fprintf( stderr, "DRM version 1.%d too old to support HyperZ, " "disabling.\n", sPriv->drm_version.minor ); -@@ -291,59 +324,21 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual, +@@ -291,59 +331,15 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual, r200InitTextureFuncs(&functions); r200InitShaderFuncs(&functions); @@ -879,7 +907,12 @@ index c067515..10a6362 100644 - if (!rmesa->glCtx) { - FREE(rmesa); - return GL_FALSE; -- } ++ if (!radeonInitContext(&rmesa->radeon, &functions, ++ glVisual, driContextPriv, ++ sharedContextPrivate)) { ++ FREE(rmesa); ++ return GL_FALSE; + } - driContextPriv->driverPrivate = rmesa; - - /* Init r200 context data */ @@ -913,21 +946,12 @@ index c067515..10a6362 100644 - & rmesa->swapped, - sizeof( r200TexObj ), - (destroy_texture_object_t *) r200DestroyTexObj ); -+ if (!radeonInitContext(&rmesa->radeon, &functions, -+ glVisual, driContextPriv, -+ sharedContextPrivate)) { -+ FREE(rmesa); -+ return GL_FALSE; - } +- } - rmesa->texture_depth = driQueryOptioni (&rmesa->optionCache, -+ -+ rmesa->radeon.texture_depth = driQueryOptioni (&rmesa->radeon.optionCache, - "texture_depth"); +- "texture_depth"); - if (rmesa->texture_depth == DRI_CONF_TEXTURE_DEPTH_FB) - rmesa->texture_depth = ( screen->cpp == 4 ) ? -+ if (rmesa->radeon.texture_depth == DRI_CONF_TEXTURE_DEPTH_FB) -+ rmesa->radeon.texture_depth = ( screen->cpp == 4 ) ? - DRI_CONF_TEXTURE_DEPTH_32 : DRI_CONF_TEXTURE_DEPTH_16; +- DRI_CONF_TEXTURE_DEPTH_32 : DRI_CONF_TEXTURE_DEPTH_16; - rmesa->swtcl.RenderIndex = ~0; - rmesa->hw.all_dirty = 1; @@ -936,7 +960,7 @@ index c067515..10a6362 100644 /* Set the maximum texture size small enough that we can guarentee that * all texture units can bind a maximal texture and have all of them in -@@ -351,29 +346,13 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual, +@@ -351,29 +347,13 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual, * setting allow larger textures. */ @@ -969,7 +993,7 @@ index c067515..10a6362 100644 ctx->Const.MaxTextureMaxAnisotropy = 16.0; -@@ -383,7 +362,7 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual, +@@ -383,7 +363,7 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual, ctx->Const.MinPointSizeAA = 1.0; ctx->Const.MaxPointSizeAA = 1.0; ctx->Const.PointSizeGranularity = 0.0625; @@ -978,11 +1002,14 @@ index c067515..10a6362 100644 ctx->Const.MaxPointSize = 2047.0; else ctx->Const.MaxPointSize = 1.0; -@@ -439,32 +418,32 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual, +@@ -439,32 +419,35 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual, _math_matrix_set_identity( &rmesa->tmpmat ); driInitExtensions( ctx, card_extensions, GL_TRUE ); - if (!(rmesa->r200Screen->chip_flags & R200_CHIPSET_YCBCR_BROKEN)) { ++ ++ if (rmesa->radeon.radeonScreen->kernel_mm) ++ driInitExtensions(ctx, mm_extensions, GL_FALSE); + if (!(rmesa->radeon.radeonScreen->chip_flags & R200_CHIPSET_YCBCR_BROKEN)) { /* yuv textures don't work with some chips - R200 / rv280 okay so far others get the bit ordering right but don't actually do YUV-RGB conversion */ @@ -1020,10 +1047,11 @@ index c067515..10a6362 100644 driInitExtensions( ctx, point_extensions, GL_FALSE ); #if 0 r200InitDriverFuncs( ctx ); -@@ -474,33 +453,15 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual, +@@ -474,33 +457,16 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual, #endif /* plug in a few more device driver functions */ /* XXX these should really go right after _mesa_init_driver_functions() */ ++ radeon_fbo_init(&rmesa->radeon); + radeonInitSpanFuncs( ctx ); r200InitPixelFuncs( ctx ); - r200InitSpanFuncs( ctx ); @@ -1055,7 +1083,7 @@ index c067515..10a6362 100644 #if DO_DEBUG R200_DEBUG = driParseDebugString( getenv( "R200_DEBUG" ), debug_control ); -@@ -508,18 +469,18 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual, +@@ -508,18 +474,18 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual, debug_control ); #endif @@ -1080,7 +1108,7 @@ index c067515..10a6362 100644 } return GL_TRUE; -@@ -538,55 +499,33 @@ void r200DestroyContext( __DRIcontextPrivate *driContextPriv ) +@@ -538,55 +504,33 @@ void r200DestroyContext( __DRIcontextPrivate *driContextPriv ) /* check if we're deleting the currently bound context */ if (rmesa == current) { @@ -1093,23 +1121,23 @@ index c067515..10a6362 100644 assert(rmesa); /* should never be null */ if ( rmesa ) { - GLboolean release_texture_heaps; -- + ++ _swsetup_DestroyContext( rmesa->radeon.glCtx ); ++ _tnl_DestroyContext( rmesa->radeon.glCtx ); ++ _vbo_DestroyContext( rmesa->radeon.glCtx ); ++ _swrast_DestroyContext( rmesa->radeon.glCtx ); - release_texture_heaps = (rmesa->glCtx->Shared->RefCount == 1); - _swsetup_DestroyContext( rmesa->glCtx ); - _tnl_DestroyContext( rmesa->glCtx ); - _vbo_DestroyContext( rmesa->glCtx ); - _swrast_DestroyContext( rmesa->glCtx ); -+ _swsetup_DestroyContext( rmesa->radeon.glCtx ); -+ _tnl_DestroyContext( rmesa->radeon.glCtx ); -+ _vbo_DestroyContext( rmesa->radeon.glCtx ); -+ _swrast_DestroyContext( rmesa->radeon.glCtx ); - -- r200DestroySwtcl( rmesa->glCtx ); -- r200ReleaseArrays( rmesa->glCtx, ~0 ); + r200DestroySwtcl( rmesa->radeon.glCtx ); + r200ReleaseArrays( rmesa->radeon.glCtx, ~0 ); +- r200DestroySwtcl( rmesa->glCtx ); +- r200ReleaseArrays( rmesa->glCtx, ~0 ); +- - if (rmesa->dma.current.buf) { - r200ReleaseDmaRegion( rmesa, &rmesa->dma.current, __FUNCTION__ ); - r200FlushCmdBuf( rmesa, __FUNCTION__ ); @@ -1121,8 +1149,11 @@ index c067515..10a6362 100644 - if (rmesa->state.scissor.pClipRects) { - FREE(rmesa->state.scissor.pClipRects); - rmesa->state.scissor.pClipRects = NULL; -- } -- ++ if (rmesa->radeon.state.scissor.pClipRects) { ++ FREE(rmesa->radeon.state.scissor.pClipRects); ++ rmesa->radeon.state.scissor.pClipRects = NULL; + } + - if ( release_texture_heaps ) { - /* This share group is about to go away, free our private - * texture object data. @@ -1135,11 +1166,8 @@ index c067515..10a6362 100644 - } - - assert( is_empty_list( & rmesa->swapped ) ); -+ if (rmesa->radeon.state.scissor.pClipRects) { -+ FREE(rmesa->radeon.state.scissor.pClipRects); -+ rmesa->radeon.state.scissor.pClipRects = NULL; - } - +- } +- - /* free the Mesa context */ - rmesa->glCtx->DriverCtx = NULL; - _mesa_destroy_context( rmesa->glCtx ); @@ -1150,7 +1178,7 @@ index c067515..10a6362 100644 FREE( rmesa ); } -@@ -594,107 +533,6 @@ void r200DestroyContext( __DRIcontextPrivate *driContextPriv ) +@@ -594,107 +538,6 @@ void r200DestroyContext( __DRIcontextPrivate *driContextPriv ) @@ -1258,7 +1286,7 @@ index c067515..10a6362 100644 /* Force the context `c' to be unbound from its buffer. */ GLboolean -@@ -703,7 +541,7 @@ r200UnbindContext( __DRIcontextPrivate *driContextPriv ) +@@ -703,7 +546,7 @@ r200UnbindContext( __DRIcontextPrivate *driContextPriv ) r200ContextPtr rmesa = (r200ContextPtr) driContextPriv->driverPrivate; if (R200_DEBUG & DEBUG_DRI) @@ -1268,7 +1296,7 @@ index c067515..10a6362 100644 return GL_TRUE; } diff --git a/src/mesa/drivers/dri/r200/r200_context.h b/src/mesa/drivers/dri/r200/r200_context.h -index 14a1dda..f7bad2a 100644 +index 14a1dda..fcbe725 100644 --- a/src/mesa/drivers/dri/r200/r200_context.h +++ b/src/mesa/drivers/dri/r200/r200_context.h @@ -53,51 +53,17 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. @@ -1639,23 +1667,23 @@ index 14a1dda..f7bad2a 100644 - * installed in the Mesa state vector. - */ - GLuint vertex_size; -- + - /** - * Attributes instructing the Mesa TCL pipeline where / how to put vertex - * data in the hardware buffer. - */ - struct tnl_attr_map vertex_attrs[VERT_ATTRIB_MAX]; -- + - /** - * Number of elements of \c ::vertex_attrs that are actually used. - */ - GLuint vertex_attr_count; - +- - /** - * Cached pointer to the buffer where Mesa will store vertex data. - */ - GLubyte *verts; - +- - /* Fallback rasterization functions - */ - r200_point_func draw_point; @@ -1785,7 +1813,7 @@ index 14a1dda..f7bad2a 100644 /* r200_tcl.c */ struct r200_tcl_info tcl; -@@ -910,45 +617,34 @@ struct r200_context { +@@ -910,14 +617,6 @@ struct r200_context { */ struct r200_swtcl_info swtcl; @@ -1800,18 +1828,9 @@ index 14a1dda..f7bad2a 100644 GLboolean using_hyperz; GLboolean texmicrotile; - struct ati_fragment_shader *afs_loaded; --}; +@@ -927,28 +626,10 @@ struct r200_context { + #define R200_CONTEXT(ctx) ((r200ContextPtr)(ctx->DriverCtx)) --#define R200_CONTEXT(ctx) ((r200ContextPtr)(ctx->DriverCtx)) -+ struct { -+ struct gl_fragment_program *bitmap_fp; -+ struct gl_vertex_program *passthrough_vp; - -+ struct gl_fragment_program *saved_fp; -+ GLboolean saved_fp_enable; -+ struct gl_vertex_program *saved_vp; -+ GLboolean saved_vp_enable; -static INLINE GLuint r200PackColor( GLuint cpp, - GLubyte r, GLubyte g, @@ -1826,16 +1845,8 @@ index 14a1dda..f7bad2a 100644 - return 0; - } -} -+ GLint saved_vp_x, saved_vp_y; -+ GLsizei saved_vp_width, saved_vp_height; -+ GLenum saved_matrix_mode; -+ } meta; -+ -+}; -+ -+#define R200_CONTEXT(ctx) ((r200ContextPtr)(ctx->DriverCtx)) - - +- +- extern void r200DestroyContext( __DRIcontextPrivate *driContextPriv ); extern GLboolean r200CreateContext( const __GLcontextModes *glVisual, __DRIcontextPrivate *driContextPriv, @@ -1846,7 +1857,7 @@ index 14a1dda..f7bad2a 100644 extern GLboolean r200MakeCurrent( __DRIcontextPrivate *driContextPriv, __DRIdrawablePrivate *driDrawPriv, __DRIdrawablePrivate *driReadPriv ); -@@ -957,28 +653,9 @@ extern GLboolean r200UnbindContext( __DRIcontextPrivate *driContextPriv ); +@@ -957,28 +638,9 @@ extern GLboolean r200UnbindContext( __DRIcontextPrivate *driContextPriv ); /* ================================================================ * Debugging: */ @@ -1891,33 +1902,21 @@ index d514b28..85c1b7b 100644 } } diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.c b/src/mesa/drivers/dri/r200/r200_ioctl.c -index 0741e57..96ed496 100644 +index 0741e57..ccb5620 100644 --- a/src/mesa/drivers/dri/r200/r200_ioctl.c +++ b/src/mesa/drivers/dri/r200/r200_ioctl.c -@@ -41,6 +41,22 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +@@ -41,6 +41,10 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "main/context.h" #include "swrast/swrast.h" -+#include "main/blend.h" -+#include "main/bufferobj.h" -+#include "main/buffers.h" -+#include "main/depth.h" -+#include "main/shaders.h" -+#include "main/texstate.h" -+#include "main/varray.h" -+#include "glapi/dispatch.h" -+#include "swrast/swrast.h" -+#include "main/stencil.h" -+#include "main/matrix.h" -+#include "main/attrib.h" -+#include "main/enable.h" ++ + +#include "radeon_common.h" +#include "radeon_lock.h" #include "r200_context.h" #include "r200_state.h" #include "r200_ioctl.h" -@@ -54,635 +70,230 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +@@ -54,635 +58,19 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define R200_TIMEOUT 512 #define R200_IDLE_RETRY 16 @@ -1931,31 +1930,18 @@ index 0741e57..96ed496 100644 - * start of a cmdbuf can rely on the state being kept from the previous one. - */ -static void r200BackUpAndEmitLostStateLocked( r200ContextPtr rmesa ) -+static void -+r200_meta_set_passthrough_transform(r200ContextPtr r200) - { +-{ - GLuint nr_released_bufs; - struct r200_store saved_store; -+ GLcontext *ctx = r200->radeon.glCtx; - +- - if (rmesa->backup_store.cmd_used == 0) - return; -+ r200->meta.saved_vp_x = ctx->Viewport.X; -+ r200->meta.saved_vp_y = ctx->Viewport.Y; -+ r200->meta.saved_vp_width = ctx->Viewport.Width; -+ r200->meta.saved_vp_height = ctx->Viewport.Height; -+ r200->meta.saved_matrix_mode = ctx->Transform.MatrixMode; - +- - if (R200_DEBUG & DEBUG_STATE) - fprintf(stderr, "Emitting backup state on lost context\n"); -+ _mesa_Viewport(0, 0, ctx->DrawBuffer->Width, ctx->DrawBuffer->Height); - +- - rmesa->lost_context = GL_FALSE; -+ _mesa_MatrixMode(GL_PROJECTION); -+ _mesa_PushMatrix(); -+ _mesa_LoadIdentity(); -+ _mesa_Ortho(0, ctx->DrawBuffer->Width, 0, ctx->DrawBuffer->Height, 1, -1); - +- - nr_released_bufs = rmesa->dma.nr_released_bufs; - saved_store = rmesa->store; - rmesa->dma.nr_released_bufs = 0; @@ -1963,15 +1949,10 @@ index 0741e57..96ed496 100644 - r200FlushCmdBufLocked( rmesa, __FUNCTION__ ); - rmesa->dma.nr_released_bufs = nr_released_bufs; - rmesa->store = saved_store; -+ _mesa_MatrixMode(GL_MODELVIEW); -+ _mesa_PushMatrix(); -+ _mesa_LoadIdentity(); - } - +-} +- -int r200FlushCmdBufLocked( r200ContextPtr rmesa, const char * caller ) -+static void -+r200_meta_restore_transform(r200ContextPtr r200) - { +-{ - int ret, i; - drm_radeon_cmd_buffer_t cmd; - @@ -2015,13 +1996,8 @@ index 0741e57..96ed496 100644 - "mangled textures\n", __FUNCTION__ ); - } - } -+ _mesa_MatrixMode(GL_PROJECTION); -+ _mesa_PopMatrix(); -+ _mesa_MatrixMode(GL_MODELVIEW); -+ _mesa_PopMatrix(); - -+ _mesa_MatrixMode(r200->meta.saved_matrix_mode); - +- +- - cmd.bufsz = rmesa->store.cmd_used; - cmd.buf = rmesa->store.cmd_buf; - @@ -2054,10 +2030,8 @@ index 0741e57..96ed496 100644 - rmesa->save_on_next_emit = 1; - - return ret; -+ _mesa_Viewport(r200->meta.saved_vp_x, r200->meta.saved_vp_y, -+ r200->meta.saved_vp_width, r200->meta.saved_vp_height); - } - +-} +- - -/* Note: does not emit any commands to avoid recursion on - * r200AllocCmdBuf. @@ -2081,19 +2055,11 @@ index 0741e57..96ed496 100644 - -/* ============================================================= - * Hardware vertex buffer handling -+/** -+ * Perform glClear where mask contains only color, depth, and/or stencil. -+ * -+ * The implementation is based on calling into Mesa to set GL state and -+ * performing normal triangle rendering. The intent of this path is to -+ * have as generic a path as possible, so that any driver could make use of -+ * it. - */ +- */ - - -void r200RefillCurrentDmaRegion( r200ContextPtr rmesa ) -+static void radeon_clear_tris(GLcontext *ctx, GLbitfield mask) - { +-{ - struct r200_dma_buffer *dmabuf; - int fd = rmesa->dri.fd; - int index = 0; @@ -2131,16 +2097,7 @@ index 0741e57..96ed496 100644 - ret = drmDMA( fd, &dma ); - if (ret == 0) - break; -+ r200ContextPtr rmesa = R200_CONTEXT(ctx); -+ GLfloat vertices[4][3]; -+ GLfloat color[4][4]; -+ GLfloat dst_z; -+ struct gl_framebuffer *fb = ctx->DrawBuffer; -+ int i; -+ GLboolean saved_fp_enable = GL_FALSE, saved_vp_enable = GL_FALSE; -+ GLboolean saved_shader_program = 0; -+ unsigned int saved_active_texture; - +- - if (rmesa->dma.nr_released_bufs) { - r200FlushCmdBufLocked( rmesa, __FUNCTION__ ); - } @@ -2150,46 +2107,7 @@ index 0741e57..96ed496 100644 - DO_USLEEP( 1 ); - LOCK_HARDWARE( rmesa ); - } -+ assert((mask & ~(BUFFER_BIT_BACK_LEFT | BUFFER_BIT_FRONT_LEFT | -+ BUFFER_BIT_DEPTH | BUFFER_BIT_STENCIL)) == 0); -+ -+ _mesa_PushAttrib(GL_COLOR_BUFFER_BIT | -+ GL_CURRENT_BIT | -+ GL_DEPTH_BUFFER_BIT | -+ GL_ENABLE_BIT | -+ GL_STENCIL_BUFFER_BIT | -+ GL_TRANSFORM_BIT | -+ GL_CURRENT_BIT); -+ _mesa_PushClientAttrib(GL_CLIENT_VERTEX_ARRAY_BIT); -+ saved_active_texture = ctx->Texture.CurrentUnit; -+ -+ /* Disable existing GL state we don't want to apply to a clear. */ -+ _mesa_Disable(GL_ALPHA_TEST); -+ _mesa_Disable(GL_BLEND); -+ _mesa_Disable(GL_CULL_FACE); -+ _mesa_Disable(GL_FOG); -+ _mesa_Disable(GL_POLYGON_SMOOTH); -+ _mesa_Disable(GL_POLYGON_STIPPLE); -+ _mesa_Disable(GL_POLYGON_OFFSET_FILL); -+ _mesa_Disable(GL_LIGHTING); -+ _mesa_Disable(GL_CLIP_PLANE0); -+ _mesa_Disable(GL_CLIP_PLANE1); -+ _mesa_Disable(GL_CLIP_PLANE2); -+ _mesa_Disable(GL_CLIP_PLANE3); -+ _mesa_Disable(GL_CLIP_PLANE4); -+ _mesa_Disable(GL_CLIP_PLANE5); -+ if (ctx->Extensions.ARB_fragment_program && ctx->FragmentProgram.Enabled) { -+ saved_fp_enable = GL_TRUE; -+ _mesa_Disable(GL_FRAGMENT_PROGRAM_ARB); -+ } -+ if (ctx->Extensions.ARB_vertex_program && ctx->VertexProgram.Enabled) { -+ saved_vp_enable = GL_TRUE; -+ _mesa_Disable(GL_VERTEX_PROGRAM_ARB); -+ } -+ if (ctx->Extensions.ARB_shader_objects && ctx->Shader.CurrentProgram) { -+ saved_shader_program = ctx->Shader.CurrentProgram->Name; -+ _mesa_UseProgramObjectARB(0); - } +- } - - UNLOCK_HARDWARE(rmesa); - @@ -2213,7 +2131,7 @@ index 0741e57..96ed496 100644 -{ - if (R200_DEBUG & DEBUG_IOCTL) - fprintf(stderr, "%s from %s\n", __FUNCTION__, caller); - +- - if (!region->buf) - return; - @@ -2226,9 +2144,7 @@ index 0741e57..96ed496 100644 - if (R200_DEBUG & (DEBUG_IOCTL|DEBUG_DMA)) - fprintf(stderr, "%s -- DISCARD BUF %d\n", __FUNCTION__, - region->buf->buf->idx); -+ if (ctx->Texture._EnabledUnits != 0) { -+ int i; - +- - cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, sizeof(*cmd), - __FUNCTION__ ); - cmd->dma.cmd_type = RADEON_CMD_DMA_DISCARD; @@ -2346,19 +2262,7 @@ index 0741e57..96ed496 100644 - UNLOCK_HARDWARE( rmesa ); - r200WaitIrq( rmesa ); - LOCK_HARDWARE( rmesa ); -+ for (i = 0; i < ctx->Const.MaxTextureUnits; i++) { -+ _mesa_ActiveTextureARB(GL_TEXTURE0 + i); -+ _mesa_Disable(GL_TEXTURE_1D); -+ _mesa_Disable(GL_TEXTURE_2D); -+ _mesa_Disable(GL_TEXTURE_3D); -+ if (ctx->Extensions.ARB_texture_cube_map) -+ _mesa_Disable(GL_TEXTURE_CUBE_MAP_ARB); -+ if (ctx->Extensions.NV_texture_rectangle) -+ _mesa_Disable(GL_TEXTURE_RECTANGLE_NV); -+ if (ctx->Extensions.MESA_texture_array) { -+ _mesa_Disable(GL_TEXTURE_1D_ARRAY_EXT); -+ _mesa_Disable(GL_TEXTURE_2D_ARRAY_EXT); - } +- } - rmesa->irqsEmitted = 10; - } - @@ -2373,8 +2277,8 @@ index 0741e57..96ed496 100644 - if (rmesa->do_usleeps) - DO_USLEEP( 1 ); - LOCK_HARDWARE( rmesa ); - } - } +- } +- } -} - - @@ -2398,16 +2302,8 @@ index 0741e57..96ed496 100644 - - if ( R200_DEBUG & DEBUG_IOCTL ) { - fprintf( stderr, "\n%s( %p )\n\n", __FUNCTION__, (void *)rmesa->glCtx ); -+ -+ r200_meta_set_passthrough_transform(rmesa); -+ -+ for (i = 0; i < 4; i++) { -+ color[i][0] = ctx->Color.ClearColor[0]; -+ color[i][1] = ctx->Color.ClearColor[1]; -+ color[i][2] = ctx->Color.ClearColor[2]; -+ color[i][3] = ctx->Color.ClearColor[3]; - } - +- } +- - R200_FIREVERTICES( rmesa ); - - LOCK_HARDWARE( rmesa ); @@ -2415,12 +2311,7 @@ index 0741e57..96ed496 100644 - - /* Throttle the frame rate -- only allow one pending swap buffers - * request at a time. -+ /* convert clear Z from [0,1] to NDC coord in [-1,1] */ -+ dst_z = -1.0 + 2.0 * ctx->Depth.Clear; -+ -+ /* Prepare the vertices, which are the same regardless of which buffer we're -+ * drawing to. - */ +- */ - r200WaitForFrameCompletion( rmesa ); - if (!rect) - { @@ -2455,118 +2346,56 @@ index 0741e57..96ed496 100644 - if (b->x1 >= b->x2 || b->y1 >= b->y2) - continue; - } -+ vertices[0][0] = fb->_Xmin; -+ vertices[0][1] = fb->_Ymin; -+ vertices[0][2] = dst_z; -+ vertices[1][0] = fb->_Xmax; -+ vertices[1][1] = fb->_Ymin; -+ vertices[1][2] = dst_z; -+ vertices[2][0] = fb->_Xmax; -+ vertices[2][1] = fb->_Ymax; -+ vertices[2][2] = dst_z; -+ vertices[3][0] = fb->_Xmin; -+ vertices[3][1] = fb->_Ymax; -+ vertices[3][2] = dst_z; -+ -+ _mesa_ColorPointer(4, GL_FLOAT, 4 * sizeof(GLfloat), &color); -+ _mesa_VertexPointer(3, GL_FLOAT, 3 * sizeof(GLfloat), &vertices); -+ _mesa_Enable(GL_COLOR_ARRAY); -+ _mesa_Enable(GL_VERTEX_ARRAY); -+ -+ while (mask != 0) { -+ GLuint this_mask = 0; -+ -+ if (mask & BUFFER_BIT_BACK_LEFT) -+ this_mask = BUFFER_BIT_BACK_LEFT; -+ else if (mask & BUFFER_BIT_FRONT_LEFT) -+ this_mask = BUFFER_BIT_FRONT_LEFT; -+ -+ /* Clear depth/stencil in the same pass as color. */ -+ this_mask |= (mask & (BUFFER_BIT_DEPTH | BUFFER_BIT_STENCIL)); -+ -+ /* Select the current color buffer and use the color write mask if -+ * we have one, otherwise don't write any color channels. -+ */ -+ if (this_mask & BUFFER_BIT_FRONT_LEFT) -+ _mesa_DrawBuffer(GL_FRONT_LEFT); -+ else if (this_mask & BUFFER_BIT_BACK_LEFT) -+ _mesa_DrawBuffer(GL_BACK_LEFT); -+ else -+ _mesa_ColorMask(GL_FALSE, GL_FALSE, GL_FALSE, GL_FALSE); - +- - b++; - n++; -+ /* Control writing of the depth clear value to depth. */ -+ if (this_mask & BUFFER_BIT_DEPTH) { -+ _mesa_DepthFunc(GL_ALWAYS); -+ _mesa_Enable(GL_DEPTH_TEST); -+ } else { -+ _mesa_Disable(GL_DEPTH_TEST); -+ _mesa_DepthMask(GL_FALSE); - } +- } - rmesa->sarea->nbox = n; - - if (!n) - continue; - +- - ret = drmCommandNone( rmesa->dri.fd, DRM_RADEON_SWAP ); - - if ( ret ) { - fprintf( stderr, "DRM_R200_SWAP_BUFFERS: return = %d\n", ret ); - UNLOCK_HARDWARE( rmesa ); - exit( 1 ); -+ /* Control writing of the stencil clear value to stencil. */ -+ if (this_mask & BUFFER_BIT_STENCIL) { -+ _mesa_Enable(GL_STENCIL_TEST); -+ _mesa_StencilOp(GL_REPLACE, GL_REPLACE, GL_REPLACE); -+ _mesa_StencilFuncSeparate(GL_FRONT, GL_ALWAYS, ctx->Stencil.Clear, -+ ctx->Stencil.WriteMask[0]); -+ } else { -+ _mesa_Disable(GL_STENCIL_TEST); - } +- } - } - - UNLOCK_HARDWARE( rmesa ); - if (!rect) - { - rmesa->hw.all_dirty = GL_TRUE; - +- - rmesa->swap_count++; - (*psp->systemTime->getUST)( & ust ); - if ( missed_target ) { - rmesa->swap_missed_count++; - rmesa->swap_missed_ust = ust - rmesa->swap_ust; - } -+ CALL_DrawArrays(ctx->Exec, (GL_TRIANGLE_FAN, 0, 4)); - +- - rmesa->swap_ust = ust; - - sched_yield(); -+ mask &= ~this_mask; - } +- } -} - +- -void r200PageFlip( __DRIdrawablePrivate *dPriv ) --{ ++static void r200UserClear(GLcontext *ctx, GLuint mask) + { - r200ContextPtr rmesa; - GLint ret; - GLboolean missed_target; - __DRIscreenPrivate *psp = dPriv->driScreenPriv; -+ r200_meta_restore_transform(rmesa); - +- - assert(dPriv); - assert(dPriv->driContextPriv); - assert(dPriv->driContextPriv->driverPrivate); -+ _mesa_ActiveTextureARB(GL_TEXTURE0 + saved_active_texture); -+ if (saved_fp_enable) -+ _mesa_Enable(GL_FRAGMENT_PROGRAM_ARB); -+ if (saved_vp_enable) -+ _mesa_Enable(GL_VERTEX_PROGRAM_ARB); - +- - rmesa = (r200ContextPtr) dPriv->driContextPriv->driverPrivate; -+ if (saved_shader_program) -+ _mesa_UseProgramObjectARB(saved_shader_program); - +- - if ( R200_DEBUG & DEBUG_IOCTL ) { - fprintf(stderr, "%s: pfCurrentPage: %d\n", __FUNCTION__, - rmesa->sarea->pfCurrentPage); @@ -2636,15 +2465,10 @@ index 0741e57..96ed496 100644 - */ - driFlipRenderbuffers(rmesa->glCtx->WinSysDrawBuffer, - rmesa->sarea->pfCurrentPage); -+ _mesa_PopClientAttrib(); -+ _mesa_PopAttrib(); -+} - - +- +- - r200UpdateDrawBuffer(rmesa->glCtx); -#endif -+static void r200UserClear(GLcontext *ctx, GLuint mask) -+{ + radeon_clear_tris(ctx, mask); } @@ -2672,7 +2496,10 @@ index 0741e57..96ed496 100644 - if ( dPriv->numClipRects == 0 ) - return; - } -- ++ __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable; ++ GLint cx, cy, cw, ch, ret; ++ GLuint i; + - r200Flush( ctx ); - - if ( mask & BUFFER_BIT_FRONT_LEFT ) { @@ -2716,10 +2543,7 @@ index 0741e57..96ed496 100644 - flags |= RADEON_CLEAR_FASTZ; - } - } -+ __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable; -+ GLint cx, cy, cw, ch, ret; -+ GLuint i; - +- - LOCK_HARDWARE( rmesa ); - - /* compute region after locking: */ @@ -2735,7 +2559,7 @@ index 0741e57..96ed496 100644 /* Throttle the number of clear ioctls we do. */ -@@ -693,7 +304,7 @@ static void r200Clear( GLcontext *ctx, GLbitfield mask ) +@@ -693,7 +81,7 @@ static void r200Clear( GLcontext *ctx, GLbitfield mask ) gp.param = RADEON_PARAM_LAST_CLEAR; gp.value = (int *)&clear; @@ -2744,7 +2568,7 @@ index 0741e57..96ed496 100644 DRM_RADEON_GETPARAM, &gp, sizeof(gp) ); if ( ret ) { -@@ -703,24 +314,34 @@ static void r200Clear( GLcontext *ctx, GLbitfield mask ) +@@ -703,24 +91,34 @@ static void r200Clear( GLcontext *ctx, GLbitfield mask ) /* Clear throttling needs more thought. */ @@ -2785,7 +2609,7 @@ index 0741e57..96ed496 100644 drm_radeon_clear_t clear; drm_radeon_clear_rect_t depth_boxes[RADEON_NR_SAREA_CLIPRECTS]; GLint n = 0; -@@ -755,17 +376,17 @@ static void r200Clear( GLcontext *ctx, GLbitfield mask ) +@@ -755,17 +153,17 @@ static void r200Clear( GLcontext *ctx, GLbitfield mask ) } } @@ -2808,7 +2632,7 @@ index 0741e57..96ed496 100644 for ( ; n >= 0 ; n-- ) { depth_boxes[n].f[CLEAR_X1] = (float)b[n].x1; depth_boxes[n].f[CLEAR_Y1] = (float)b[n].y1; -@@ -774,83 +395,92 @@ static void r200Clear( GLcontext *ctx, GLbitfield mask ) +@@ -774,83 +172,91 @@ static void r200Clear( GLcontext *ctx, GLbitfield mask ) depth_boxes[n].f[CLEAR_DEPTH] = ctx->Depth.Clear; } @@ -2907,7 +2731,7 @@ index 0741e57..96ed496 100644 - if (rmesa->store.cmd_used) - r200FlushCmdBuf( rmesa, __FUNCTION__ ); -} -+ if ( (mask & BUFFER_BIT_STENCIL) && rmesa->radeon.state.stencil.hwBuffer ) { ++ if ( (mask & BUFFER_BIT_STENCIL) ) { + flags |= RADEON_STENCIL; + mask &= ~BUFFER_BIT_STENCIL; + } @@ -2924,21 +2748,20 @@ index 0741e57..96ed496 100644 + fprintf(stderr, "%s: swrast clear, mask: %x\n", __FUNCTION__, mask); + _swrast_Clear( ctx, mask ); + } -+ -+ if ( !flags ) -+ return; - if (rmesa->do_irqs) { - LOCK_HARDWARE( rmesa ); - r200EmitIrqLocked( rmesa ); - UNLOCK_HARDWARE( rmesa ); - r200WaitIrq( rmesa ); ++ if ( !flags ) ++ return; ++ + if (rmesa->using_hyperz) { + flags |= RADEON_USE_COMP_ZBUF; +/* if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200) + flags |= RADEON_USE_HIERZ; */ -+ if (!(rmesa->radeon.state.stencil.hwBuffer) || -+ ((flags & RADEON_DEPTH) && (flags & RADEON_STENCIL) && ++ if (!((flags & RADEON_DEPTH) && (flags & RADEON_STENCIL) && + ((rmesa->radeon.state.stencil.clear & R200_STENCIL_WRITE_MASK) == R200_STENCIL_WRITE_MASK))) { + flags |= RADEON_CLEAR_FASTZ; + } @@ -2957,7 +2780,7 @@ index 0741e57..96ed496 100644 /* This version of AllocateMemoryMESA allocates only GART memory, and * only does so after the point at which the driver has been -@@ -875,7 +505,7 @@ void *r200AllocateMemoryMESA(__DRIscreen *screen, GLsizei size, +@@ -875,7 +281,7 @@ void *r200AllocateMemoryMESA(__DRIscreen *screen, GLsizei size, fprintf(stderr, "%s sz %d %f/%f/%f\n", __FUNCTION__, size, readfreq, writefreq, priority); @@ -2966,7 +2789,7 @@ index 0741e57..96ed496 100644 return NULL; if (getenv("R200_NO_ALLOC")) -@@ -886,7 +516,7 @@ void *r200AllocateMemoryMESA(__DRIscreen *screen, GLsizei size, +@@ -886,7 +292,7 @@ void *r200AllocateMemoryMESA(__DRIscreen *screen, GLsizei size, alloc.size = size; alloc.region_offset = ®ion_offset; @@ -2975,7 +2798,7 @@ index 0741e57..96ed496 100644 DRM_RADEON_ALLOC, &alloc, sizeof(alloc)); -@@ -896,7 +526,7 @@ void *r200AllocateMemoryMESA(__DRIscreen *screen, GLsizei size, +@@ -896,7 +302,7 @@ void *r200AllocateMemoryMESA(__DRIscreen *screen, GLsizei size, } { @@ -2984,7 +2807,7 @@ index 0741e57..96ed496 100644 return (void *)(region_start + region_offset); } } -@@ -914,24 +544,24 @@ void r200FreeMemoryMESA(__DRIscreen *screen, GLvoid *pointer) +@@ -914,24 +320,24 @@ void r200FreeMemoryMESA(__DRIscreen *screen, GLvoid *pointer) if (R200_DEBUG & DEBUG_IOCTL) fprintf(stderr, "%s %p\n", __FUNCTION__, pointer); @@ -3014,7 +2837,7 @@ index 0741e57..96ed496 100644 DRM_RADEON_FREE, &memfree, sizeof(memfree)); -@@ -956,16 +586,16 @@ GLuint r200GetMemoryOffsetMESA(__DRIscreen *screen, const GLvoid *pointer) +@@ -956,16 +362,16 @@ GLuint r200GetMemoryOffsetMESA(__DRIscreen *screen, const GLvoid *pointer) card_offset = r200GartOffsetFromVirtual( rmesa, pointer ); @@ -3034,7 +2857,7 @@ index 0741e57..96ed496 100644 if (R200_DEBUG & DEBUG_IOCTL) fprintf(stderr, "r200IsGartMemory( %p ) : %d\n", pointer, valid ); -@@ -976,12 +606,12 @@ GLboolean r200IsGartMemory( r200ContextPtr rmesa, const GLvoid *pointer, +@@ -976,12 +382,12 @@ GLboolean r200IsGartMemory( r200ContextPtr rmesa, const GLvoid *pointer, GLuint r200GartOffsetFromVirtual( r200ContextPtr rmesa, const GLvoid *pointer ) { @@ -3050,7 +2873,7 @@ index 0741e57..96ed496 100644 } -@@ -989,7 +619,7 @@ GLuint r200GartOffsetFromVirtual( r200ContextPtr rmesa, const GLvoid *pointer ) +@@ -989,7 +395,7 @@ GLuint r200GartOffsetFromVirtual( r200ContextPtr rmesa, const GLvoid *pointer ) void r200InitIoctlFuncs( struct dd_function_table *functions ) { functions->Clear = r200Clear; @@ -4528,7 +4351,7 @@ index bae5644..0000000 - -#endif diff --git a/src/mesa/drivers/dri/r200/r200_state.c b/src/mesa/drivers/dri/r200/r200_state.c -index 0eaaaf6..5eb61c8 100644 +index 0eaaaf6..ca4dee8 100644 --- a/src/mesa/drivers/dri/r200/r200_state.c +++ b/src/mesa/drivers/dri/r200/r200_state.c @@ -47,6 +47,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. @@ -4703,16 +4526,17 @@ index 0eaaaf6..5eb61c8 100644 ctx->Color.ColorMask[RCOMP], ctx->Color.ColorMask[GCOMP], ctx->Color.ColorMask[BCOMP], -@@ -834,7 +740,7 @@ static void r200PolygonOffset( GLcontext *ctx, +@@ -834,7 +740,8 @@ static void r200PolygonOffset( GLcontext *ctx, GLfloat factor, GLfloat units ) { r200ContextPtr rmesa = R200_CONTEXT(ctx); - float_ui32_type constant = { units * rmesa->state.depth.scale }; -+ float_ui32_type constant = { units * rmesa->radeon.state.depth.scale }; ++ const GLfloat depthScale = 1.0F / ctx->DrawBuffer->_DepthMaxF; ++ float_ui32_type constant = { units * depthScale }; float_ui32_type factoru = { factor }; /* factor *= 2; */ -@@ -861,15 +767,15 @@ static void r200PolygonStipple( GLcontext *ctx, const GLubyte *mask ) +@@ -861,15 +768,15 @@ static void r200PolygonStipple( GLcontext *ctx, const GLubyte *mask ) /* TODO: push this into cmd mechanism */ @@ -4732,7 +4556,7 @@ index 0eaaaf6..5eb61c8 100644 } static void r200PolygonMode( GLcontext *ctx, GLenum face, GLenum mode ) -@@ -881,7 +787,7 @@ static void r200PolygonMode( GLcontext *ctx, GLenum face, GLenum mode ) +@@ -881,7 +788,7 @@ static void r200PolygonMode( GLcontext *ctx, GLenum face, GLenum mode ) * cases work. */ TCL_FALLBACK( ctx, R200_TCL_FALLBACK_UNFILLED, flag); @@ -4741,7 +4565,7 @@ index 0eaaaf6..5eb61c8 100644 r200ChooseRenderState( ctx ); r200ChooseVertexState( ctx ); } -@@ -958,7 +864,7 @@ static void r200UpdateSpecular( GLcontext *ctx ) +@@ -958,7 +865,7 @@ static void r200UpdateSpecular( GLcontext *ctx ) /* Update vertex/render formats */ @@ -4750,7 +4574,7 @@ index 0eaaaf6..5eb61c8 100644 r200ChooseRenderState( ctx ); r200ChooseVertexState( ctx ); } -@@ -1430,7 +1336,7 @@ static void r200LightModelfv( GLcontext *ctx, GLenum pname, +@@ -1430,7 +1337,7 @@ static void r200LightModelfv( GLcontext *ctx, GLenum pname, rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] |= R200_LIGHT_TWOSIDE; else rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] &= ~(R200_LIGHT_TWOSIDE); @@ -4759,7 +4583,7 @@ index 0eaaaf6..5eb61c8 100644 r200ChooseRenderState( ctx ); r200ChooseVertexState( ctx ); } -@@ -1675,7 +1581,7 @@ static void r200ClearStencil( GLcontext *ctx, GLint s ) +@@ -1675,7 +1582,7 @@ static void r200ClearStencil( GLcontext *ctx, GLint s ) { r200ContextPtr rmesa = R200_CONTEXT(ctx); @@ -4768,7 +4592,7 @@ index 0eaaaf6..5eb61c8 100644 ((GLuint) (ctx->Stencil.Clear & 0xff) | (0xff << R200_STENCIL_MASK_SHIFT) | ((ctx->Stencil.WriteMask[0] & 0xff) << R200_STENCIL_WRITEMASK_SHIFT)); -@@ -1700,19 +1606,18 @@ static void r200ClearStencil( GLcontext *ctx, GLint s ) +@@ -1700,19 +1607,29 @@ static void r200ClearStencil( GLcontext *ctx, GLint s ) void r200UpdateWindow( GLcontext *ctx ) { r200ContextPtr rmesa = R200_CONTEXT(ctx); @@ -4779,21 +4603,34 @@ index 0eaaaf6..5eb61c8 100644 + GLfloat xoffset = dPriv ? (GLfloat) dPriv->x : 0; + GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0; const GLfloat *v = ctx->Viewport._WindowMap.m; ++ const GLboolean render_to_fbo = (ctx->DrawBuffer ? (ctx->DrawBuffer->Name != 0) : 0); ++ const GLfloat depthScale = 1.0F / ctx->DrawBuffer->_DepthMaxF; ++ GLfloat y_scale, y_bias; ++ ++ if (render_to_fbo) { ++ y_scale = 1.0; ++ y_bias = 0; ++ } else { ++ y_scale = -1.0; ++ y_bias = yoffset; ++ } float_ui32_type sx = { v[MAT_SX] }; float_ui32_type tx = { v[MAT_TX] + xoffset + SUBPIXEL_X }; - float_ui32_type sy = { - v[MAT_SY] }; - float_ui32_type ty = { (- v[MAT_TY]) + yoffset + SUBPIXEL_Y }; +- float_ui32_type sy = { - v[MAT_SY] }; +- float_ui32_type ty = { (- v[MAT_TY]) + yoffset + SUBPIXEL_Y }; - float_ui32_type sz = { v[MAT_SZ] * rmesa->state.depth.scale }; - float_ui32_type tz = { v[MAT_TZ] * rmesa->state.depth.scale }; -+ float_ui32_type sz = { v[MAT_SZ] * rmesa->radeon.state.depth.scale }; -+ float_ui32_type tz = { v[MAT_TZ] * rmesa->radeon.state.depth.scale }; ++ float_ui32_type sy = { v[MAT_SY] * y_scale }; ++ float_ui32_type ty = { (v[MAT_TY] * y_scale) + y_bias + SUBPIXEL_Y }; ++ float_ui32_type sz = { v[MAT_SZ] * depthScale }; ++ float_ui32_type tz = { v[MAT_TZ] * depthScale }; - R200_FIREVERTICES( rmesa ); R200_STATECHANGE( rmesa, vpt ); rmesa->hw.vpt.cmd[VPT_SE_VPORT_XSCALE] = sx.ui32; -@@ -1733,6 +1638,8 @@ static void r200Viewport( GLcontext *ctx, GLint x, GLint y, +@@ -1733,6 +1650,8 @@ static void r200Viewport( GLcontext *ctx, GLint x, GLint y, * values, or keep the originals hanging around. */ r200UpdateWindow( ctx ); @@ -4802,7 +4639,7 @@ index 0eaaaf6..5eb61c8 100644 } static void r200DepthRange( GLcontext *ctx, GLclampd nearval, -@@ -1744,7 +1651,7 @@ static void r200DepthRange( GLcontext *ctx, GLclampd nearval, +@@ -1744,7 +1663,7 @@ static void r200DepthRange( GLcontext *ctx, GLclampd nearval, void r200UpdateViewportOffset( GLcontext *ctx ) { r200ContextPtr rmesa = R200_CONTEXT(ctx); @@ -4811,7 +4648,7 @@ index 0eaaaf6..5eb61c8 100644 GLfloat xoffset = (GLfloat)dPriv->x; GLfloat yoffset = (GLfloat)dPriv->y + dPriv->h; const GLfloat *v = ctx->Viewport._WindowMap.m; -@@ -1774,8 +1681,8 @@ void r200UpdateViewportOffset( GLcontext *ctx ) +@@ -1774,8 +1693,8 @@ void r200UpdateViewportOffset( GLcontext *ctx ) R200_STIPPLE_Y_OFFSET_MASK); /* add magic offsets, then invert */ @@ -4822,7 +4659,7 @@ index 0eaaaf6..5eb61c8 100644 & R200_STIPPLE_COORD_MASK); m |= ((stx << R200_STIPPLE_X_OFFSET_SHIFT) | -@@ -1788,7 +1695,7 @@ void r200UpdateViewportOffset( GLcontext *ctx ) +@@ -1788,7 +1707,7 @@ void r200UpdateViewportOffset( GLcontext *ctx ) } } @@ -4831,7 +4668,7 @@ index 0eaaaf6..5eb61c8 100644 } -@@ -1805,7 +1712,7 @@ static void r200ClearColor( GLcontext *ctx, const GLfloat c[4] ) +@@ -1805,7 +1724,7 @@ static void r200ClearColor( GLcontext *ctx, const GLfloat c[4] ) CLAMPED_FLOAT_TO_UBYTE(color[1], c[1]); CLAMPED_FLOAT_TO_UBYTE(color[2], c[2]); CLAMPED_FLOAT_TO_UBYTE(color[3], c[3]); @@ -4840,7 +4677,7 @@ index 0eaaaf6..5eb61c8 100644 color[0], color[1], color[2], color[3] ); } -@@ -1848,96 +1755,6 @@ static void r200LogicOpCode( GLcontext *ctx, GLenum opcode ) +@@ -1848,96 +1767,6 @@ static void r200LogicOpCode( GLcontext *ctx, GLenum opcode ) rmesa->hw.msk.cmd[MSK_RB3D_ROPCNTL] = r200_rop_tab[rop]; } @@ -4937,7 +4774,7 @@ index 0eaaaf6..5eb61c8 100644 /* ============================================================= * State enable/disable */ -@@ -2013,10 +1830,10 @@ static void r200Enable( GLcontext *ctx, GLenum cap, GLboolean state ) +@@ -2013,10 +1842,10 @@ static void r200Enable( GLcontext *ctx, GLenum cap, GLboolean state ) R200_STATECHANGE(rmesa, ctx ); if ( state ) { rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_DITHER_ENABLE; @@ -4950,7 +4787,7 @@ index 0eaaaf6..5eb61c8 100644 } break; -@@ -2031,7 +1848,7 @@ static void r200Enable( GLcontext *ctx, GLenum cap, GLboolean state ) +@@ -2031,7 +1860,7 @@ static void r200Enable( GLcontext *ctx, GLenum cap, GLboolean state ) rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] &= ~R200_TCL_FOG_MASK; } r200UpdateSpecular( ctx ); /* for PK_SPEC */ @@ -4959,7 +4796,7 @@ index 0eaaaf6..5eb61c8 100644 r200ChooseVertexState( ctx ); _mesa_allow_light_in_model( ctx, !state ); break; -@@ -2068,7 +1885,7 @@ static void r200Enable( GLcontext *ctx, GLenum cap, GLboolean state ) +@@ -2068,7 +1897,7 @@ static void r200Enable( GLcontext *ctx, GLenum cap, GLboolean state ) case GL_LIGHTING: r200UpdateSpecular(ctx); /* for reflection map fixup - might set recheck_texgen for all units too */ @@ -4968,7 +4805,7 @@ index 0eaaaf6..5eb61c8 100644 break; case GL_LINE_SMOOTH: -@@ -2181,13 +1998,13 @@ static void r200Enable( GLcontext *ctx, GLenum cap, GLboolean state ) +@@ -2181,21 +2010,30 @@ static void r200Enable( GLcontext *ctx, GLenum cap, GLboolean state ) } case GL_SCISSOR_TEST: @@ -4982,11 +4819,34 @@ index 0eaaaf6..5eb61c8 100644 case GL_STENCIL_TEST: - if ( rmesa->state.stencil.hwBuffer ) { -+ if ( rmesa->radeon.state.stencil.hwBuffer ) { - R200_STATECHANGE( rmesa, ctx ); - if ( state ) { - rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_STENCIL_ENABLE; -@@ -2432,64 +2249,88 @@ static void update_texturematrix( GLcontext *ctx ) +- R200_STATECHANGE( rmesa, ctx ); +- if ( state ) { +- rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_STENCIL_ENABLE; ++ { ++ GLboolean hw_stencil = GL_FALSE; ++ if (ctx->DrawBuffer) { ++ struct radeon_renderbuffer *rrbStencil ++ = radeon_get_renderbuffer(ctx->DrawBuffer, BUFFER_STENCIL); ++ hw_stencil = (rrbStencil && rrbStencil->bo); ++ } ++ ++ if (hw_stencil) { ++ R200_STATECHANGE( rmesa, ctx ); ++ if ( state ) { ++ rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_STENCIL_ENABLE; ++ } else { ++ rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~R200_STENCIL_ENABLE; ++ } + } else { +- rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~R200_STENCIL_ENABLE; ++ FALLBACK( rmesa, R200_FALLBACK_STENCIL, state ); + } +- } else { +- FALLBACK( rmesa, R200_FALLBACK_STENCIL, state ); + } + break; + +@@ -2432,64 +2270,88 @@ static void update_texturematrix( GLcontext *ctx ) } } @@ -5116,7 +4976,7 @@ index 0eaaaf6..5eb61c8 100644 /* FIXME: don't really need most of these when vertex progs are enabled */ /* Need an event driven matrix update? -@@ -2533,7 +2374,8 @@ void r200ValidateState( GLcontext *ctx ) +@@ -2533,7 +2395,8 @@ void r200ValidateState( GLcontext *ctx ) else TCL_FALLBACK(ctx, R200_TCL_FALLBACK_VERTEX_PROGRAM, 0); } @@ -5126,7 +4986,7 @@ index 0eaaaf6..5eb61c8 100644 } -@@ -2544,7 +2386,7 @@ static void r200InvalidateState( GLcontext *ctx, GLuint new_state ) +@@ -2544,7 +2407,7 @@ static void r200InvalidateState( GLcontext *ctx, GLuint new_state ) _vbo_InvalidateState( ctx, new_state ); _tnl_InvalidateState( ctx, new_state ); _ae_invalidate_state( ctx, new_state ); @@ -5135,7 +4995,7 @@ index 0eaaaf6..5eb61c8 100644 } /* A hack. The r200 can actually cope just fine with materials -@@ -2573,12 +2415,13 @@ static void r200WrapRunPipeline( GLcontext *ctx ) +@@ -2573,12 +2436,13 @@ static void r200WrapRunPipeline( GLcontext *ctx ) GLboolean has_material; if (0) @@ -5152,7 +5012,7 @@ index 0eaaaf6..5eb61c8 100644 has_material = !ctx->VertexProgram._Enabled && ctx->Light.Enabled && check_material( ctx ); -@@ -2603,8 +2446,8 @@ void r200InitStateFuncs( struct dd_function_table *functions ) +@@ -2603,8 +2467,8 @@ void r200InitStateFuncs( struct dd_function_table *functions ) functions->UpdateState = r200InvalidateState; functions->LightingSpaceChange = r200LightingSpaceChange; @@ -5163,7 +5023,7 @@ index 0eaaaf6..5eb61c8 100644 functions->AlphaFunc = r200AlphaFunc; functions->BlendColor = r200BlendColor; -@@ -2636,7 +2479,7 @@ void r200InitStateFuncs( struct dd_function_table *functions ) +@@ -2636,7 +2500,7 @@ void r200InitStateFuncs( struct dd_function_table *functions ) functions->PointParameterfv = r200PointParameter; functions->PointSize = r200PointSize; functions->RenderMode = r200RenderMode; @@ -5201,7 +5061,7 @@ index a917163..1dddbfd 100644 extern void r200LightingSpaceChange( GLcontext *ctx ); diff --git a/src/mesa/drivers/dri/r200/r200_state_init.c b/src/mesa/drivers/dri/r200/r200_state_init.c -index 9e4677e..a71f33c 100644 +index 9e4677e..30326c2 100644 --- a/src/mesa/drivers/dri/r200/r200_state_init.c +++ b/src/mesa/drivers/dri/r200/r200_state_init.c @@ -43,6 +43,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. @@ -5366,7 +5226,7 @@ index 9e4677e..a71f33c 100644 return h.i; } -@@ -127,150 +243,480 @@ static int cmdscl2( int offset, int stride, int count ) +@@ -127,150 +243,474 @@ static int cmdscl2( int offset, int stride, int count ) } #define CHECK( NM, FLAG ) \ @@ -5499,9 +5359,15 @@ index 9e4677e..a71f33c 100644 + OUT_SCL2(atom->cmd[MTL_CMD_1], (atom->cmd + 18)); + END_BATCH(); +} -+ + +-/* Initialize the context's hardware state. +- */ +-void r200InitState( r200ContextPtr rmesa ) +static void lit_emit(GLcontext *ctx, struct radeon_state_atom *atom) -+{ + { +- GLcontext *ctx = rmesa->glCtx; +- GLuint color_fmt, depth_fmt, i; +- GLint drawPitch, drawOffset; + r200ContextPtr r200 = R200_CONTEXT(ctx); + BATCH_LOCALS(&r200->radeon); + uint32_t dwords = atom->cmd_size; @@ -5512,7 +5378,17 @@ index 9e4677e..a71f33c 100644 + OUT_VEC(atom->cmd[LIT_CMD_1], atom->cmd+LIT_CMD_1+1); + END_BATCH(); +} -+ + +- switch ( rmesa->r200Screen->cpp ) { +- case 2: +- color_fmt = R200_COLOR_FORMAT_RGB565; +- break; +- case 4: +- color_fmt = R200_COLOR_FORMAT_ARGB8888; +- break; +- default: +- fprintf( stderr, "Error: Unsupported pixel depth... exiting\n" ); +- exit( -1 ); +static void ptp_emit(GLcontext *ctx, struct radeon_state_atom *atom) +{ + r200ContextPtr r200 = R200_CONTEXT(ctx); @@ -5611,10 +5487,28 @@ index 9e4677e..a71f33c 100644 + + OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]); + OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); -+ } -+ + } + +- rmesa->state.color.clear = 0x00000000; + OUT_BATCH(atom->cmd[CTX_CMD_2]); -+ + +- switch ( ctx->Visual.depthBits ) { +- case 16: +- rmesa->state.depth.clear = 0x0000ffff; +- rmesa->state.depth.scale = 1.0 / (GLfloat)0xffff; +- depth_fmt = R200_DEPTH_FORMAT_16BIT_INT_Z; +- rmesa->state.stencil.clear = 0x00000000; +- break; +- case 24: +- rmesa->state.depth.clear = 0x00ffffff; +- rmesa->state.depth.scale = 1.0 / (GLfloat)0xffffff; +- depth_fmt = R200_DEPTH_FORMAT_24BIT_INT_Z; +- rmesa->state.stencil.clear = 0xffff0000; +- break; +- default: +- fprintf( stderr, "Error: Unsupported depth %d... exiting\n", +- ctx->Visual.depthBits ); +- exit( -1 ); + if (!rrb || !rrb->bo) { + OUT_BATCH(atom->cmd[CTX_RB3D_COLORPITCH]); + } else { @@ -5622,14 +5516,24 @@ index 9e4677e..a71f33c 100644 + if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) + cbpitch |= R200_COLOR_TILE_ENABLE; + OUT_BATCH(cbpitch); -+ } -+ + } + +- /* Only have hw stencil when depth buffer is 24 bits deep */ +- rmesa->state.stencil.hwBuffer = ( ctx->Visual.stencilBits > 0 && +- ctx->Visual.depthBits == 24 ); + if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM) + OUT_BATCH_TABLE((atom->cmd + 14), 4); -+ + +- rmesa->Fallback = 0; + END_BATCH(); +} -+ + +- if ( ctx->Visual.doubleBufferMode && rmesa->sarea->pfCurrentPage == 0 ) { +- drawOffset = rmesa->r200Screen->backOffset; +- drawPitch = rmesa->r200Screen->backPitch; +- } else { +- drawOffset = rmesa->r200Screen->frontOffset; +- drawPitch = rmesa->r200Screen->frontPitch; +static void ctx_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom) +{ + r200ContextPtr r200 = R200_CONTEXT(ctx); @@ -5685,7 +5589,11 @@ index 9e4677e..a71f33c 100644 + + OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHPITCH, 0)); + OUT_BATCH(zbpitch); -+ } + } +-#if 000 +- if ( ctx->Visual.doubleBufferMode && rmesa->sarea->pfCurrentPage == 0 ) { +- rmesa->state.color.drawOffset = rmesa->r200Screen->backOffset; +- rmesa->state.color.drawPitch = rmesa->r200Screen->backPitch; + + OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZSTENCILCNTL, 0)); + OUT_BATCH(atom->cmd[CTX_RB3D_ZSTENCILCNTL]); @@ -5735,13 +5643,19 @@ index 9e4677e..a71f33c 100644 + } else if (!t) { + /* workaround for old CS mechanism */ + OUT_BATCH(r200->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]); -+ } else { + } else { +- rmesa->state.color.drawOffset = rmesa->r200Screen->frontOffset; +- rmesa->state.color.drawPitch = rmesa->r200Screen->frontPitch; + OUT_BATCH(t->override_offset); -+ } -+ + } + +- rmesa->state.pixel.readOffset = rmesa->state.color.drawOffset; +- rmesa->state.pixel.readPitch = rmesa->state.color.drawPitch; +-#endif + END_BATCH(); +} -+ + +- rmesa->hw.max_state_size = 0; +static void tex_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom) +{ + r200ContextPtr r200 = R200_CONTEXT(ctx); @@ -5812,87 +5726,30 @@ index 9e4677e..a71f33c 100644 + } + END_BATCH(); +} - - /* Initialize the context's hardware state. - */ - void r200InitState( r200ContextPtr rmesa ) - { -- GLcontext *ctx = rmesa->glCtx; -- GLuint color_fmt, depth_fmt, i; -- GLint drawPitch, drawOffset; ++ ++/* Initialize the context's hardware state. ++ */ ++void r200InitState( r200ContextPtr rmesa ) ++{ + GLcontext *ctx = rmesa->radeon.glCtx; + GLuint i; - -- switch ( rmesa->r200Screen->cpp ) { -- case 2: -- color_fmt = R200_COLOR_FORMAT_RGB565; -- break; -- case 4: -- color_fmt = R200_COLOR_FORMAT_ARGB8888; -- break; -- default: -- fprintf( stderr, "Error: Unsupported pixel depth... exiting\n" ); -- exit( -1 ); -- } -- -- rmesa->state.color.clear = 0x00000000; ++ + rmesa->radeon.state.color.clear = 0x00000000; - - switch ( ctx->Visual.depthBits ) { - case 16: -- rmesa->state.depth.clear = 0x0000ffff; -- rmesa->state.depth.scale = 1.0 / (GLfloat)0xffff; -- depth_fmt = R200_DEPTH_FORMAT_16BIT_INT_Z; -- rmesa->state.stencil.clear = 0x00000000; ++ ++ switch ( ctx->Visual.depthBits ) { ++ case 16: + rmesa->radeon.state.depth.clear = 0x0000ffff; -+ rmesa->radeon.state.depth.scale = 1.0 / (GLfloat)0xffff; + rmesa->radeon.state.stencil.clear = 0x00000000; - break; - case 24: -- rmesa->state.depth.clear = 0x00ffffff; -- rmesa->state.depth.scale = 1.0 / (GLfloat)0xffffff; -- depth_fmt = R200_DEPTH_FORMAT_24BIT_INT_Z; -- rmesa->state.stencil.clear = 0xffff0000; -- break; - default: -- fprintf( stderr, "Error: Unsupported depth %d... exiting\n", -- ctx->Visual.depthBits ); -- exit( -1 ); ++ break; ++ case 24: ++ default: + rmesa->radeon.state.depth.clear = 0x00ffffff; -+ rmesa->radeon.state.depth.scale = 1.0 / (GLfloat)0xffffff; + rmesa->radeon.state.stencil.clear = 0xffff0000; + break; - } - - /* Only have hw stencil when depth buffer is 24 bits deep */ -- rmesa->state.stencil.hwBuffer = ( ctx->Visual.stencilBits > 0 && -+ rmesa->radeon.state.stencil.hwBuffer = ( ctx->Visual.stencilBits > 0 && - ctx->Visual.depthBits == 24 ); - -- rmesa->Fallback = 0; -- -- if ( ctx->Visual.doubleBufferMode && rmesa->sarea->pfCurrentPage == 0 ) { -- drawOffset = rmesa->r200Screen->backOffset; -- drawPitch = rmesa->r200Screen->backPitch; -- } else { -- drawOffset = rmesa->r200Screen->frontOffset; -- drawPitch = rmesa->r200Screen->frontPitch; -- } --#if 000 -- if ( ctx->Visual.doubleBufferMode && rmesa->sarea->pfCurrentPage == 0 ) { -- rmesa->state.color.drawOffset = rmesa->r200Screen->backOffset; -- rmesa->state.color.drawPitch = rmesa->r200Screen->backPitch; -- } else { -- rmesa->state.color.drawOffset = rmesa->r200Screen->frontOffset; -- rmesa->state.color.drawPitch = rmesa->r200Screen->frontPitch; -- } -- -- rmesa->state.pixel.readOffset = rmesa->state.color.drawOffset; -- rmesa->state.pixel.readPitch = rmesa->state.color.drawPitch; --#endif ++ } ++ + rmesa->radeon.Fallback = 0; - -- rmesa->hw.max_state_size = 0; ++ + rmesa->radeon.hw.max_state_size = 0; #define ALLOC_STATE( ATOM, CHK, SZ, NM, IDX ) \ @@ -5926,7 +5783,7 @@ index 9e4677e..a71f33c 100644 ALLOC_STATE( set, always, SET_STATE_SIZE, "SET/setup", 0 ); ALLOC_STATE( lin, always, LIN_STATE_SIZE, "LIN/line", 0 ); ALLOC_STATE( msk, always, MSK_STATE_SIZE, "MSK/mask", 0 ); -@@ -282,8 +728,8 @@ void r200InitState( r200ContextPtr rmesa ) +@@ -282,8 +722,8 @@ void r200InitState( r200ContextPtr rmesa ) ALLOC_STATE( cst, always, CST_STATE_SIZE, "CST/constant", 0 ); ALLOC_STATE( zbs, always, ZBS_STATE_SIZE, "ZBS/zbias", 0 ); ALLOC_STATE( tf, tf, TF_STATE_SIZE, "TF/tfactor", 0 ); @@ -5937,7 +5794,7 @@ index 9e4677e..a71f33c 100644 /* make sure texture units 0/1 are emitted pair-wise for r200 t0 hang workaround */ ALLOC_STATE( tex[0], tex_pair, TEX_STATE_SIZE_NEWDRM, "TEX/tex-0", 0 ); ALLOC_STATE( tex[1], tex_pair, TEX_STATE_SIZE_NEWDRM, "TEX/tex-1", 1 ); -@@ -303,7 +749,7 @@ void r200InitState( r200ContextPtr rmesa ) +@@ -303,7 +743,7 @@ void r200InitState( r200ContextPtr rmesa ) ALLOC_STATE( afs[1], afs, AFS_STATE_SIZE, "AFS/afsinst-1", 1 ); } else { @@ -5946,7 +5803,7 @@ index 9e4677e..a71f33c 100644 ALLOC_STATE( tex[0], tex_pair, TEX_STATE_SIZE_OLDDRM, "TEX/tex-0", 0 ); ALLOC_STATE( tex[1], tex_pair, TEX_STATE_SIZE_OLDDRM, "TEX/tex-1", 1 ); ALLOC_STATE( tam, tex_any, TAM_STATE_SIZE, "TAM/tam", 0 ); -@@ -321,13 +767,21 @@ void r200InitState( r200ContextPtr rmesa ) +@@ -321,13 +761,21 @@ void r200InitState( r200ContextPtr rmesa ) ALLOC_STATE( afs[0], never, AFS_STATE_SIZE, "AFS/afsinst-0", 0 ); ALLOC_STATE( afs[1], never, AFS_STATE_SIZE, "AFS/afsinst-1", 1 ); } @@ -5969,7 +5826,7 @@ index 9e4677e..a71f33c 100644 } else { ALLOC_STATE( cube[0], never, CUBE_STATE_SIZE, "CUBE/tex-0", 0 ); -@@ -337,7 +791,8 @@ void r200InitState( r200ContextPtr rmesa ) +@@ -337,7 +785,8 @@ void r200InitState( r200ContextPtr rmesa ) ALLOC_STATE( cube[4], never, CUBE_STATE_SIZE, "CUBE/tex-4", 4 ); ALLOC_STATE( cube[5], never, CUBE_STATE_SIZE, "CUBE/tex-5", 5 ); } @@ -5979,7 +5836,7 @@ index 9e4677e..a71f33c 100644 ALLOC_STATE( pvs, tcl_vp, PVS_STATE_SIZE, "PVS/pvscntl", 0 ); ALLOC_STATE( vpi[0], tcl_vp, VPI_STATE_SIZE, "VP/vertexprog-0", 0 ); ALLOC_STATE( vpi[1], tcl_vp_size, VPI_STATE_SIZE, "VP/vertexprog-1", 1 ); -@@ -390,13 +845,13 @@ void r200InitState( r200ContextPtr rmesa ) +@@ -390,13 +839,13 @@ void r200InitState( r200ContextPtr rmesa ) ALLOC_STATE( pix[3], texenv, PIX_STATE_SIZE, "PIX/pixstage-3", 3 ); ALLOC_STATE( pix[4], texenv, PIX_STATE_SIZE, "PIX/pixstage-4", 4 ); ALLOC_STATE( pix[5], texenv, PIX_STATE_SIZE, "PIX/pixstage-5", 5 ); @@ -5995,7 +5852,7 @@ index 9e4677e..a71f33c 100644 ALLOC_STATE( spr, always, SPR_STATE_SIZE, "SPR/pointsprite", 0 ); ALLOC_STATE( ptp, tcl, PTP_STATE_SIZE, "PTP/pointparams", 0 ); } -@@ -409,87 +864,115 @@ void r200InitState( r200ContextPtr rmesa ) +@@ -409,87 +858,115 @@ void r200InitState( r200ContextPtr rmesa ) /* Fill in the packet headers: */ @@ -6191,7 +6048,7 @@ index 9e4677e..a71f33c 100644 rmesa->hw.mtl[0].cmd[MTL_CMD_0] = cmdvec( R200_VS_MAT_0_EMISS, 1, 16 ); rmesa->hw.mtl[0].cmd[MTL_CMD_1] = -@@ -567,7 +1050,7 @@ void r200InitState( r200ContextPtr rmesa ) +@@ -567,7 +1044,7 @@ void r200InitState( r200ContextPtr rmesa ) (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) | (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT)); @@ -6200,7 +6057,7 @@ index 9e4677e..a71f33c 100644 rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCOLOR] = 0x00000000; rmesa->hw.ctx.cmd[CTX_RB3D_ABLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP | (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) | -@@ -578,18 +1061,17 @@ void r200InitState( r200ContextPtr rmesa ) +@@ -578,18 +1055,17 @@ void r200InitState( r200ContextPtr rmesa ) } rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHOFFSET] = @@ -6222,7 +6079,7 @@ index 9e4677e..a71f33c 100644 R200_STENCIL_TEST_ALWAYS | R200_STENCIL_FAIL_KEEP | R200_STENCIL_ZPASS_KEEP | -@@ -599,15 +1081,14 @@ void r200InitState( r200ContextPtr rmesa ) +@@ -599,15 +1075,14 @@ void r200InitState( r200ContextPtr rmesa ) if (rmesa->using_hyperz) { rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_Z_COMPRESSION_ENABLE | R200_Z_DECOMPRESSION_ENABLE; @@ -6240,7 +6097,7 @@ index 9e4677e..a71f33c 100644 case DRI_CONF_DITHER_XERRORDIFFRESET: rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_DITHER_INIT; break; -@@ -615,41 +1096,19 @@ void r200InitState( r200ContextPtr rmesa ) +@@ -615,41 +1090,19 @@ void r200InitState( r200ContextPtr rmesa ) rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_SCALE_DITHER_ENABLE; break; } @@ -6288,7 +6145,7 @@ index 9e4677e..a71f33c 100644 rmesa->hw.prf.cmd[PRF_PP_PERF_CNTL] = 0; rmesa->hw.set.cmd[SET_SE_CNTL] = (R200_FFACE_CULL_CCW | -@@ -704,7 +1163,7 @@ void r200InitState( r200ContextPtr rmesa ) +@@ -704,7 +1157,7 @@ void r200InitState( r200ContextPtr rmesa ) R200_VC_NO_SWAP; #endif @@ -6297,7 +6154,7 @@ index 9e4677e..a71f33c 100644 /* Bypass TCL */ rmesa->hw.cst.cmd[CST_SE_VAP_CNTL_STATUS] |= (1<<8); } -@@ -743,28 +1202,28 @@ void r200InitState( r200ContextPtr rmesa ) +@@ -743,28 +1196,28 @@ void r200InitState( r200ContextPtr rmesa ) rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT_X] = (/* R200_TEXCOORD_PROJ | */ 0x100000); /* Small default bias */ @@ -6334,7 +6191,7 @@ index 9e4677e..a71f33c 100644 rmesa->hw.pix[i].cmd[PIX_PP_TXCBLEND] = (R200_TXC_ARG_A_ZERO | -@@ -967,5 +1426,7 @@ void r200InitState( r200ContextPtr rmesa ) +@@ -967,5 +1420,7 @@ void r200InitState( r200ContextPtr rmesa ) r200LightingSpaceChange( ctx ); @@ -9449,7 +9306,7 @@ index a2561df..aadd144 100644 R200_STATECHANGE( rmesa, vap ); /* FIXME: fglrx sets R200_VAP_SINGLE_BUF_STATE_ENABLE too. Do we need it? diff --git a/src/mesa/drivers/dri/r300/Makefile b/src/mesa/drivers/dri/r300/Makefile -index 6ca9342..497b1ec 100644 +index 6ca9342..0dff9a1 100644 --- a/src/mesa/drivers/dri/r300/Makefile +++ b/src/mesa/drivers/dri/r300/Makefile @@ -3,6 +3,8 @@ @@ -9461,7 +9318,7 @@ index 6ca9342..497b1ec 100644 LIBNAME = r300_dri.so MINIGLX_SOURCES = server/radeon_dri.c -@@ -20,20 +22,24 @@ COMMON_SOURCES = \ +@@ -20,20 +22,25 @@ COMMON_SOURCES = \ ../common/xmlconfig.c \ ../common/dri_util.c @@ -9474,7 +9331,8 @@ index 6ca9342..497b1ec 100644 + radeon_bo_legacy.c \ + radeon_cs_legacy.c \ + radeon_mipmap_tree.c \ -+ radeon_span.c ++ radeon_span.c \ ++ radeon_fbo.c + DRIVER_SOURCES = \ radeon_screen.c \ @@ -9493,7 +9351,7 @@ index 6ca9342..497b1ec 100644 r300_tex.c \ r300_texstate.c \ radeon_program.c \ -@@ -49,12 +55,15 @@ DRIVER_SOURCES = \ +@@ -49,12 +56,15 @@ DRIVER_SOURCES = \ r300_shader.c \ r300_emit.c \ r300_swtcl.c \ @@ -9510,7 +9368,7 @@ index 6ca9342..497b1ec 100644 SYMLINKS = \ server/radeon_dri.c \ -@@ -68,7 +77,28 @@ COMMON_SYMLINKS = \ +@@ -68,7 +78,29 @@ COMMON_SYMLINKS = \ radeon_chipset.h \ radeon_screen.c \ radeon_screen.h \ @@ -9534,17 +9392,18 @@ index 6ca9342..497b1ec 100644 + radeon_mipmap_tree.c \ + radeon_mipmap_tree.h \ + radeon_texture.c \ -+ radeon_texture.h ++ radeon_texture.h \ ++ radeon_fbo.c + +DRI_LIB_DEPS += $(RADEON_LDFLAGS) ##### TARGETS ##### diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c -index 3eb2dc8..2c6618f 100644 +index 3eb2dc8..d85f106 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c -@@ -44,245 +44,287 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +@@ -44,245 +44,288 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "drm.h" #include "radeon_drm.h" @@ -9848,6 +9707,7 @@ index 3eb2dc8..2c6618f 100644 + BATCH_LOCALS(&r300->radeon); + struct radeon_renderbuffer *rrb; + uint32_t cbpitch; ++ uint32_t offset = r300->radeon.state.color.draw_offset; + + rrb = radeon_get_colorbuffer(&r300->radeon); + if (!rrb || !rrb->bo) { @@ -9866,7 +9726,7 @@ index 3eb2dc8..2c6618f 100644 + + BEGIN_BATCH_NO_AUTOSTATE(6); + OUT_BATCH_REGSEQ(R300_RB3D_COLOROFFSET0, 1); -+ OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); ++ OUT_BATCH_RELOC(offset, rrb->bo, offset, 0, RADEON_GEM_DOMAIN_VRAM, 0); + OUT_BATCH_REGSEQ(R300_RB3D_COLORPITCH0, 1); + OUT_BATCH(cbpitch); + END_BATCH(); @@ -10004,7 +9864,7 @@ index 3eb2dc8..2c6618f 100644 cnt = r500fp_count(atom->cmd); return cnt ? (cnt * 4) + 1 : 0; } -@@ -295,8 +337,8 @@ static int check_r500fp_const(r300ContextPtr r300, struct r300_state_atom *atom) +@@ -295,8 +338,8 @@ static int check_r500fp_const(r300ContextPtr r300, struct r300_state_atom *atom) r300->hw.ATOM.idx = (IDX); \ r300->hw.ATOM.check = check_##CHK; \ r300->hw.ATOM.dirty = GL_FALSE; \ @@ -10015,7 +9875,7 @@ index 3eb2dc8..2c6618f 100644 } while (0) /** * Allocate memory for the command buffer and initialize the state atom -@@ -304,7 +346,7 @@ static int check_r500fp_const(r300ContextPtr r300, struct r300_state_atom *atom) +@@ -304,7 +347,7 @@ static int check_r500fp_const(r300ContextPtr r300, struct r300_state_atom *atom) */ void r300InitCmdBuf(r300ContextPtr r300) { @@ -10024,7 +9884,7 @@ index 3eb2dc8..2c6618f 100644 int has_tcl = 1; int is_r500 = 0; int i; -@@ -315,7 +357,7 @@ void r300InitCmdBuf(r300ContextPtr r300) +@@ -315,7 +358,7 @@ void r300InitCmdBuf(r300ContextPtr r300) if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) is_r500 = 1; @@ -10033,7 +9893,7 @@ index 3eb2dc8..2c6618f 100644 mtu = r300->radeon.glCtx->Const.MaxTextureUnits; if (RADEON_DEBUG & DEBUG_TEXTURE) { -@@ -323,97 +365,97 @@ void r300InitCmdBuf(r300ContextPtr r300) +@@ -323,97 +366,97 @@ void r300InitCmdBuf(r300ContextPtr r300) } /* Setup the atom linked list */ @@ -10168,7 +10028,7 @@ index 3eb2dc8..2c6618f 100644 for (i = 0; i < 8; i++) { r300->hw.ri.cmd[R300_RI_CMD_0 + i +1] = (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_S_SHIFT) | -@@ -422,133 +464,149 @@ void r300InitCmdBuf(r300ContextPtr r300) +@@ -422,133 +465,149 @@ void r300InitCmdBuf(r300ContextPtr r300) (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT); } ALLOC_STATE(rr, variable, R300_RR_CMDSIZE, 0); @@ -10374,7 +10234,7 @@ index 3eb2dc8..2c6618f 100644 } } } -@@ -556,61 +614,39 @@ void r300InitCmdBuf(r300ContextPtr r300) +@@ -556,61 +615,39 @@ void r300InitCmdBuf(r300ContextPtr r300) /* Textures */ ALLOC_STATE(tex.filter, variable, mtu + 1, 0); r300->hw.tex.filter.cmd[R300_TEX_CMD_0] = @@ -10449,7 +10309,7 @@ index 3eb2dc8..2c6618f 100644 } /** -@@ -618,68 +654,10 @@ void r300InitCmdBuf(r300ContextPtr r300) +@@ -618,68 +655,10 @@ void r300InitCmdBuf(r300ContextPtr r300) */ void r300DestroyCmdBuf(r300ContextPtr r300) { @@ -10610,7 +10470,7 @@ index a8eaa58..b7798eb 100644 #endif /* __R300_CMDBUF_H__ */ diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c -index fddd87b..5bae37e 100644 +index fddd87b..87ec68a 100644 --- a/src/mesa/drivers/dri/r300/r300_context.c +++ b/src/mesa/drivers/dri/r300/r300_context.c @@ -44,6 +44,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. @@ -10644,7 +10504,45 @@ index fddd87b..5bae37e 100644 #include "vblank.h" #include "utils.h" -@@ -183,6 +182,91 @@ static const struct tnl_pipeline_stage *r300_pipeline[] = { +@@ -83,14 +82,17 @@ int hw_tcl_on = 1; + #define need_GL_EXT_blend_equation_separate + #define need_GL_EXT_blend_func_separate + #define need_GL_EXT_blend_minmax ++#define need_GL_EXT_framebuffer_object + #define need_GL_EXT_fog_coord + #define need_GL_EXT_gpu_program_parameters + #define need_GL_EXT_secondary_color + #define need_GL_EXT_stencil_two_side + #define need_GL_ATI_separate_stencil + #define need_GL_NV_vertex_program ++ + #include "extension_helper.h" + ++ + const struct dri_extension card_extensions[] = { + /* *INDENT-OFF* */ + {"GL_ARB_depth_texture", NULL}, +@@ -111,6 +113,7 @@ const struct dri_extension card_extensions[] = { + {"GL_EXT_blend_func_separate", GL_EXT_blend_func_separate_functions}, + {"GL_EXT_blend_minmax", GL_EXT_blend_minmax_functions}, + {"GL_EXT_blend_subtract", NULL}, ++ {"GL_EXT_packed_depth_stencil", NULL}, + {"GL_EXT_fog_coord", GL_EXT_fog_coord_functions }, + {"GL_EXT_gpu_program_parameters", GL_EXT_gpu_program_parameters_functions}, + {"GL_EXT_secondary_color", GL_EXT_secondary_color_functions}, +@@ -138,6 +141,11 @@ const struct dri_extension card_extensions[] = { + }; + + ++const struct dri_extension mm_extensions[] = { ++ { "GL_EXT_framebuffer_object", GL_EXT_framebuffer_object_functions }, ++ { NULL, NULL } ++}; ++ + /** + * The GL 2.0 functions are needed to make display lists work with + * functions added by GL_ATI_separate_stencil. +@@ -183,6 +191,91 @@ static const struct tnl_pipeline_stage *r300_pipeline[] = { 0, }; @@ -10736,7 +10634,7 @@ index fddd87b..5bae37e 100644 /* Create the device specific rendering context. */ GLboolean r300CreateContext(const __GLcontextModes * glVisual, -@@ -194,7 +278,7 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, +@@ -194,7 +287,7 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, struct dd_function_table functions; r300ContextPtr r300; GLcontext *ctx; @@ -10745,7 +10643,7 @@ index fddd87b..5bae37e 100644 assert(glVisual); assert(driContextPriv); -@@ -208,13 +292,14 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, +@@ -208,13 +301,14 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, if (!(screen->chip_flags & RADEON_CHIPSET_TCL)) hw_tcl_on = future_hw_tcl_on = 0; @@ -10761,7 +10659,7 @@ index fddd87b..5bae37e 100644 "def_max_anisotropy"); /* Init default driver functions then plug in our R300-specific functions -@@ -226,10 +311,6 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, +@@ -226,10 +320,6 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, r300InitTextureFuncs(&functions); r300InitShaderFuncs(&functions); @@ -10772,7 +10670,7 @@ index fddd87b..5bae37e 100644 if (!radeonInitContext(&r300->radeon, &functions, glVisual, driContextPriv, sharedContextPrivate)) { -@@ -238,37 +319,10 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, +@@ -238,39 +328,6 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, } /* Init r300 context data */ @@ -10804,16 +10702,15 @@ index fddd87b..5bae37e 100644 - /* *INDENT-ON* */ - } - r300->texture_depth = driQueryOptioni(&r300->radeon.optionCache, -+ r300->radeon.texture_depth = driQueryOptioni(&r300->radeon.optionCache, - "texture_depth"); +- "texture_depth"); - if (r300->texture_depth == DRI_CONF_TEXTURE_DEPTH_FB) - r300->texture_depth = (screen->cpp == 4) ? -+ if (r300->radeon.texture_depth == DRI_CONF_TEXTURE_DEPTH_FB) -+ r300->radeon.texture_depth = (screen->cpp == 4) ? - DRI_CONF_TEXTURE_DEPTH_32 : DRI_CONF_TEXTURE_DEPTH_16; - +- DRI_CONF_TEXTURE_DEPTH_32 : DRI_CONF_TEXTURE_DEPTH_16; +- /* Set the maximum texture size small enough that we can guarentee that -@@ -303,13 +357,11 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, + * all texture units can bind a maximal texture and have them both in + * texturable memory at once. +@@ -303,13 +360,11 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, ctx->Const.MaxLineWidth = R300_LINESIZE_MAX; ctx->Const.MaxLineWidthAA = R300_LINESIZE_MAX; @@ -10827,11 +10724,22 @@ index fddd87b..5bae37e 100644 ctx->Const.MaxDrawBuffers = 1; -@@ -384,13 +436,13 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, +@@ -365,6 +420,8 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, + ctx->FragmentProgram._MaintainTexEnvProgram = GL_TRUE; + + driInitExtensions(ctx, card_extensions, GL_TRUE); ++ if (r300->radeon.radeonScreen->kernel_mm) ++ driInitExtensions(ctx, mm_extensions, GL_FALSE); + + if (driQueryOptionb + (&r300->radeon.optionCache, "disable_stencil_two_side")) +@@ -383,14 +440,14 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, + r300->disable_lowimpact_fallback = driQueryOptionb(&r300->radeon.optionCache, "disable_lowimpact_fallback"); - +- - radeonInitSpanFuncs(ctx); ++ radeon_fbo_init(&r300->radeon); + radeonInitSpanFuncs( ctx ); r300InitCmdBuf(r300); r300InitState(r300); @@ -10843,7 +10751,7 @@ index fddd87b..5bae37e 100644 tcl_mode = driQueryOptioni(&r300->radeon.optionCache, "tcl_mode"); if (driQueryOptionb(&r300->radeon.optionCache, "no_rast")) { -@@ -413,72 +465,6 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, +@@ -413,72 +470,6 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, return GL_TRUE; } @@ -10916,7 +10824,7 @@ index fddd87b..5bae37e 100644 /* Destroy the device specific context. */ void r300DestroyContext(__DRIcontextPrivate * driContextPriv) -@@ -502,55 +488,27 @@ void r300DestroyContext(__DRIcontextPrivate * driContextPriv) +@@ -502,55 +493,27 @@ void r300DestroyContext(__DRIcontextPrivate * driContextPriv) assert(r300); /* should never be null */ if (r300) { @@ -12157,7 +12065,7 @@ index 89d7383..6bc8f8e 100644 extern int r300PrimitiveType(r300ContextPtr rmesa, int prim); extern int r300NumVerts(r300ContextPtr rmesa, int num_verts, int prim); diff --git a/src/mesa/drivers/dri/r300/r300_ioctl.c b/src/mesa/drivers/dri/r300/r300_ioctl.c -index ee85e22..d1cf579 100644 +index ee85e22..71661ee 100644 --- a/src/mesa/drivers/dri/r300/r300_ioctl.c +++ b/src/mesa/drivers/dri/r300/r300_ioctl.c @@ -46,8 +46,9 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. @@ -12171,7 +12079,7 @@ index ee85e22..d1cf579 100644 #include "r300_ioctl.h" #include "r300_cmdbuf.h" #include "r300_state.h" -@@ -55,71 +56,83 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +@@ -55,71 +56,90 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "radeon_reg.h" #include "r300_emit.h" #include "r300_fragprog.h" @@ -12186,10 +12094,17 @@ index ee85e22..d1cf579 100644 #define CLEARBUFFER_STENCIL 0x4 -static void r300ClearBuffer(r300ContextPtr r300, int flags, int buffer) ++static void r300EmitClearState(GLcontext * ctx); ++ ++static void r300UserClear(GLcontext *ctx, GLuint mask) + { ++ radeon_clear_tris(ctx, mask); ++} ++ +static void r300ClearBuffer(r300ContextPtr r300, int flags, + struct radeon_renderbuffer *rrb, + struct radeon_renderbuffer *rrbd) - { ++{ + BATCH_LOCALS(&r300->radeon); GLcontext *ctx = r300->radeon.glCtx; __DRIdrawablePrivate *dPriv = r300->radeon.dri.drawable; @@ -12300,7 +12215,7 @@ index ee85e22..d1cf579 100644 { uint32_t t1, t2; -@@ -146,37 +159,55 @@ static void r300ClearBuffer(r300ContextPtr r300, int flags, int buffer) +@@ -146,37 +166,55 @@ static void r300ClearBuffer(r300ContextPtr r300, int flags, int buffer) R300_S_FRONT_ZFAIL_OP_SHIFT); } @@ -12377,21 +12292,24 @@ index ee85e22..d1cf579 100644 int has_tcl = 1; int is_r500 = 0; GLuint vap_cntl; -@@ -184,35 +215,37 @@ static void r300EmitClearState(GLcontext * ctx) +@@ -184,35 +222,37 @@ static void r300EmitClearState(GLcontext * ctx) if (!(r300->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) has_tcl = 0; - if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) - is_r500 = 1; +- + if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) + is_r500 = 1; -- - /* FIXME: the values written to R300_VAP_INPUT_ROUTE_0_0 and - * R300_VAP_INPUT_ROUTE_0_1 are in fact known, however, the values are - * quite complex; see the functions in r300_emit.c. + /* State atom dirty tracking is a little subtle here. -+ * + * +- * I believe it would be a good idea to extend the functions in +- * r300_emit.c so that they can be used to setup the default values for +- * these registers, as well as the actual values used for rendering. + * On the one hand, we need to make sure base state is emitted + * here if we start with an empty batch buffer, otherwise clear + * works incorrectly with multiple processes. Therefore, the first @@ -12400,10 +12318,7 @@ index ee85e22..d1cf579 100644 + * On the other hand, implicit state emission clears the state atom + * dirty bits, so we have to call R300_STATECHANGE later than the + * first BEGIN_BATCH. - * -- * I believe it would be a good idea to extend the functions in -- * r300_emit.c so that they can be used to setup the default values for -- * these registers, as well as the actual values used for rendering. ++ * + * The final trickiness is that, because we change state, we need + * to ensure that any stored swtcl primitives are flushed properly + * before we start changing state. See the R300_NEWPRIM in r300Clear @@ -12436,7 +12351,7 @@ index ee85e22..d1cf579 100644 (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_SHIFT) | (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_SHIFT) | (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_SHIFT) | -@@ -226,238 +259,278 @@ static void r300EmitClearState(GLcontext * ctx) +@@ -226,619 +266,399 @@ static void r300EmitClearState(GLcontext * ctx) << R300_SWIZZLE1_SHIFT))); /* R300_VAP_INPUT_CNTL_0, R300_VAP_INPUT_CNTL_1 */ @@ -12833,12 +12748,12 @@ index ee85e22..d1cf579 100644 - R300_STATECHANGE(r300, vpi); - vsf_start_fragment(0x0, 8); -- + - e32(PVS_OP_DST_OPERAND(VE_ADD, GL_FALSE, GL_FALSE, 0, 0xf, PVS_DST_REG_OUT)); - e32(PVS_SRC_OPERAND(0, PVS_SRC_SELECT_X, PVS_SRC_SELECT_Y, PVS_SRC_SELECT_Z, PVS_SRC_SELECT_W, PVS_SRC_REG_INPUT, VSF_FLAG_NONE)); - e32(PVS_SRC_OPERAND(0, PVS_SRC_SELECT_FORCE_0, PVS_SRC_SELECT_FORCE_0, PVS_SRC_SELECT_FORCE_0, PVS_SRC_SELECT_FORCE_0, PVS_SRC_REG_INPUT, VSF_FLAG_NONE)); - e32(0x0); - +- - e32(PVS_OP_DST_OPERAND(VE_ADD, GL_FALSE, GL_FALSE, 1, 0xf, PVS_DST_REG_OUT)); - e32(PVS_SRC_OPERAND(1, PVS_SRC_SELECT_X, PVS_SRC_SELECT_Y, PVS_SRC_SELECT_Z, PVS_SRC_SELECT_W, PVS_SRC_REG_INPUT, VSF_FLAG_NONE)); - e32(PVS_SRC_OPERAND(1, PVS_SRC_SELECT_FORCE_0, PVS_SRC_SELECT_FORCE_0, PVS_SRC_SELECT_FORCE_0, PVS_SRC_SELECT_FORCE_0, PVS_SRC_REG_INPUT, VSF_FLAG_NONE)); @@ -12888,64 +12803,86 @@ index ee85e22..d1cf579 100644 } } -@@ -468,9 +541,11 @@ static void r300Clear(GLcontext * ctx, GLbitfield mask) - { +-/** +- * Buffer clear +- */ +-static void r300Clear(GLcontext * ctx, GLbitfield mask) +-{ ++static void r300KernelClear(GLcontext *ctx, GLuint flags) ++{ r300ContextPtr r300 = R300_CONTEXT(ctx); __DRIdrawablePrivate *dPriv = r300->radeon.dri.drawable; +- int flags = 0; + struct radeon_framebuffer *rfb = dPriv->driverPrivate; + struct radeon_renderbuffer *rrb; + struct radeon_renderbuffer *rrbd; - int flags = 0; int bits = 0; - int swapped; - - if (RADEON_DEBUG & DEBUG_IOCTL) - fprintf(stderr, "r300Clear\n"); -@@ -482,6 +557,12 @@ static void r300Clear(GLcontext * ctx, GLbitfield mask) - return; - } - -+ /* Flush swtcl vertices if necessary, because we will change hardware -+ * state during clear. See also the state-related comment in -+ * r300EmitClearState. -+ */ -+ R300_NEWPRIM(r300); -+ - if (mask & BUFFER_BIT_FRONT_LEFT) { - flags |= BUFFER_BIT_FRONT_LEFT; - mask &= ~BUFFER_BIT_FRONT_LEFT; -@@ -497,7 +578,7 @@ static void r300Clear(GLcontext * ctx, GLbitfield mask) - mask &= ~BUFFER_BIT_DEPTH; - } - -- if ((mask & BUFFER_BIT_STENCIL) && r300->state.stencil.hw_stencil) { -+ if ((mask & BUFFER_BIT_STENCIL) && r300->radeon.state.stencil.hwBuffer) { - bits |= CLEARBUFFER_STENCIL; - mask &= ~BUFFER_BIT_STENCIL; - } -@@ -509,336 +590,33 @@ static void r300Clear(GLcontext * ctx, GLbitfield mask) - _swrast_Clear(ctx, mask); - } - -- swapped = r300->radeon.sarea->pfCurrentPage == 1; - +- if (RADEON_DEBUG & DEBUG_IOCTL) +- fprintf(stderr, "r300Clear\n"); +- +- { +- LOCK_HARDWARE(&r300->radeon); +- UNLOCK_HARDWARE(&r300->radeon); +- if (dPriv->numClipRects == 0) +- return; +- } +- +- if (mask & BUFFER_BIT_FRONT_LEFT) { +- flags |= BUFFER_BIT_FRONT_LEFT; +- mask &= ~BUFFER_BIT_FRONT_LEFT; +- } +- +- if (mask & BUFFER_BIT_BACK_LEFT) { +- flags |= BUFFER_BIT_BACK_LEFT; +- mask &= ~BUFFER_BIT_BACK_LEFT; +- } +- +- if (mask & BUFFER_BIT_DEPTH) { +- bits |= CLEARBUFFER_DEPTH; +- mask &= ~BUFFER_BIT_DEPTH; +- } +- +- if ((mask & BUFFER_BIT_STENCIL) && r300->state.stencil.hw_stencil) { +- bits |= CLEARBUFFER_STENCIL; +- mask &= ~BUFFER_BIT_STENCIL; +- } +- +- if (mask) { +- if (RADEON_DEBUG & DEBUG_FALLBACKS) +- fprintf(stderr, "%s: swrast clear, mask: %x\n", +- __FUNCTION__, mask); +- _swrast_Clear(ctx, mask); +- } +- +- swapped = r300->radeon.sarea->pfCurrentPage == 1; + /* Make sure it fits there. */ - r300EnsureCmdBufSpace(r300, 421 * 3, __FUNCTION__); + rcommonEnsureCmdBufSpace(&r300->radeon, 421 * 3, __FUNCTION__); if (flags || bits) r300EmitClearState(ctx); -+ rrbd = (void *)rfb->base.Attachment[BUFFER_DEPTH].Renderbuffer; ++ rrbd = radeon_get_renderbuffer(&rfb->base, BUFFER_DEPTH); ++ if (rrbd && (flags & BUFFER_BIT_DEPTH)) ++ bits |= CLEARBUFFER_DEPTH; ++ if (flags & BUFFER_BIT_COLOR0) { ++ rrb = radeon_get_renderbuffer(&rfb->base, BUFFER_COLOR0); ++ r300ClearBuffer(r300, CLEARBUFFER_COLOR, rrb, NULL); ++ bits = 0; ++ } ++ if (flags & BUFFER_BIT_FRONT_LEFT) { - r300ClearBuffer(r300, bits | CLEARBUFFER_COLOR, swapped); -+ rrb = (void *)rfb->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer; ++ rrb = radeon_get_renderbuffer(&rfb->base, BUFFER_FRONT_LEFT); + r300ClearBuffer(r300, bits | CLEARBUFFER_COLOR, rrb, rrbd); bits = 0; } if (flags & BUFFER_BIT_BACK_LEFT) { - r300ClearBuffer(r300, bits | CLEARBUFFER_COLOR, swapped ^ 1); -+ rrb = (void *)rfb->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer; ++ rrb = radeon_get_renderbuffer(&rfb->base, BUFFER_BACK_LEFT); + r300ClearBuffer(r300, bits | CLEARBUFFER_COLOR, rrb, rrbd); bits = 0; } @@ -12954,13 +12891,24 @@ index ee85e22..d1cf579 100644 - r300ClearBuffer(r300, bits, 0); + r300ClearBuffer(r300, bits, NULL, rrbd); --} -- ++ COMMIT_BATCH(); + } + -void r300Flush(GLcontext * ctx) --{ ++/** ++ * Buffer clear ++ */ ++static void r300Clear(GLcontext * ctx, GLbitfield mask) + { - r300ContextPtr rmesa = R300_CONTEXT(ctx); -- -- if (RADEON_DEBUG & DEBUG_IOCTL) ++ r300ContextPtr r300 = R300_CONTEXT(ctx); ++ __DRIdrawablePrivate *dPriv = r300->radeon.dri.drawable; ++ const GLuint colorMask = *((GLuint *) & ctx->Color.ColorMask); ++ GLbitfield swrast_mask = 0, tri_mask = 0; ++ int i; ++ struct gl_framebuffer *fb = ctx->DrawBuffer; + + if (RADEON_DEBUG & DEBUG_IOCTL) - fprintf(stderr, "%s\n", __FUNCTION__); - - if (rmesa->dma.flush) @@ -12984,16 +12932,22 @@ index ee85e22..d1cf579 100644 - if (rmesa->dma.flush) { - rmesa->dma.flush(rmesa); - } -- ++ fprintf(stderr, "r300Clear\n"); + - if (rmesa->dma.current.buf) { -#ifdef USER_BUFFERS - r300_mem_use(rmesa, rmesa->dma.current.buf->id); -#endif - r300ReleaseDmaRegion(rmesa, &rmesa->dma.current, __FUNCTION__); -- } ++ if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) { ++ LOCK_HARDWARE(&r300->radeon); ++ UNLOCK_HARDWARE(&r300->radeon); ++ if (dPriv->numClipRects == 0) ++ return; + } - if (rmesa->dma.nr_released_bufs > 4) - r300FlushCmdBuf(rmesa, __FUNCTION__); -- + - dmabuf = CALLOC_STRUCT(r300_dma_buffer); - dmabuf->buf = (void *)1; /* hack */ - dmabuf->refcount = 1; @@ -13004,18 +12958,28 @@ index ee85e22..d1cf579 100644 - - r300FlushCmdBufLocked(rmesa, __FUNCTION__); - radeonWaitForIdleLocked(&rmesa->radeon); -- ++ /* Flush swtcl vertices if necessary, because we will change hardware ++ * state during clear. See also the state-related comment in ++ * r300EmitClearState. ++ */ ++ R300_NEWPRIM(r300); + - dmabuf->id = r300_mem_alloc(rmesa, 4, size); -- ++ if (colorMask == ~0) ++ tri_mask |= (mask & BUFFER_BITS_COLOR); + - UNLOCK_HARDWARE(&rmesa->radeon); -- + - if (dmabuf->id == 0) { - fprintf(stderr, - "Error: Could not get dma buffer... exiting\n"); - _mesa_exit(-1); - } -- } -- ++ /* HW stencil */ ++ if (mask & BUFFER_BIT_STENCIL) { ++ tri_mask |= BUFFER_BIT_STENCIL; + } + - rmesa->dma.current.buf = dmabuf; - rmesa->dma.current.address = r300_mem_ptr(rmesa, dmabuf->id); - rmesa->dma.current.end = size; @@ -13039,8 +13003,11 @@ index ee85e22..d1cf579 100644 - r300_mem_free(rmesa, region->buf->id); - FREE(region->buf); - rmesa->dma.nr_released_bufs++; -- } -- ++ /* HW depth */ ++ if (mask & BUFFER_BIT_DEPTH) { ++ tri_mask |= BUFFER_BIT_DEPTH; + } + - region->buf = 0; - region->start = 0; -} @@ -13081,7 +13048,10 @@ index ee85e22..d1cf579 100644 - - assert(rmesa->dma.current.ptr <= rmesa->dma.current.end); -} -- ++ /* If we're doing a tri pass for depth/stencil, include a likely color ++ * buffer with it. ++ */ + -#else -static void r300RefillCurrentDmaRegion(r300ContextPtr rmesa) -{ @@ -13097,8 +13067,16 @@ index ee85e22..d1cf579 100644 - - if (rmesa->dma.flush) { - rmesa->dma.flush(rmesa); -- } -- ++ for (i = 0; i < BUFFER_COUNT; i++) { ++ GLuint bufBit = 1 << i; ++ if ((tri_mask) & bufBit) { ++ if (!fb->Attachment[i].Renderbuffer->ClassID) { ++ tri_mask &= ~bufBit; ++ swrast_mask |= bufBit; ++ } ++ } + } + - if (rmesa->dma.current.buf) - r300ReleaseDmaRegion(rmesa, &rmesa->dma.current, __FUNCTION__); - @@ -13125,7 +13103,9 @@ index ee85e22..d1cf579 100644 - if (rmesa->dma.nr_released_bufs) { - r300FlushCmdBufLocked(rmesa, __FUNCTION__); - } -- ++ /* SW fallback clearing */ ++ swrast_mask = mask & ~tri_mask; + - if (RADEON_DEBUG & DEBUG_DMA) - fprintf(stderr, "Waiting for buffers\n"); - @@ -13138,7 +13118,12 @@ index ee85e22..d1cf579 100644 - "Error: Could not get dma buffer... exiting\n"); - _mesa_exit(-1); - } -- } ++ if (tri_mask) { ++ if (r300->radeon.radeonScreen->kernel_mm) ++ r300UserClear(ctx, tri_mask); ++ else ++ r300KernelClear(ctx, tri_mask); + } - - UNLOCK_HARDWARE(&rmesa->radeon); - @@ -13184,7 +13169,12 @@ index ee85e22..d1cf579 100644 - - FREE(region->buf); - rmesa->dma.nr_released_bufs++; -- } ++ if (swrast_mask) { ++ if (RADEON_DEBUG & DEBUG_FALLBACKS) ++ fprintf(stderr, "%s: swrast clear, mask: %x\n", ++ __FUNCTION__, swrast_mask); ++ _swrast_Clear(ctx, swrast_mask); + } - - region->buf = 0; - region->start = 0; @@ -13225,8 +13215,8 @@ index ee85e22..d1cf579 100644 - rmesa->dma.current.ptr = (rmesa->dma.current.ptr + 0x7) & ~0x7; - - assert(rmesa->dma.current.ptr <= rmesa->dma.current.end); --} -- + } + -#endif - -GLboolean r300IsGartMemory(r300ContextPtr rmesa, const GLvoid * pointer, @@ -13259,8 +13249,7 @@ index ee85e22..d1cf579 100644 - return ~0; - else - return rmesa->radeon.radeonScreen->gart_texture_offset + offset; -+ COMMIT_BATCH(); - } +-} void r300InitIoctlFuncs(struct dd_function_table *functions) { @@ -14057,7 +14046,7 @@ index 16ce4a1..402d2d7 100644 vp = (struct r300_vertex_program *)CURRENT_VERTEX_SHADER(ctx); diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c -index 8095538..f423029 100644 +index 8095538..f49b43c 100644 --- a/src/mesa/drivers/dri/r300/r300_state.c +++ b/src/mesa/drivers/dri/r300/r300_state.c @@ -53,8 +53,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. @@ -14069,29 +14058,54 @@ index 8095538..f423029 100644 #include "r300_context.h" #include "r300_ioctl.h" #include "r300_state.h" -@@ -590,7 +588,7 @@ static void r300SetStencilState(GLcontext * ctx, GLboolean state) +@@ -589,8 +587,14 @@ static void r300SetDepthState(GLcontext * ctx) + static void r300SetStencilState(GLcontext * ctx, GLboolean state) { r300ContextPtr r300 = R300_CONTEXT(ctx); ++ GLboolean hw_stencil = GL_FALSE; ++ if (ctx->DrawBuffer) { ++ struct radeon_renderbuffer *rrbStencil ++ = radeon_get_renderbuffer(ctx->DrawBuffer, BUFFER_STENCIL); ++ hw_stencil = (rrbStencil && rrbStencil->bo); ++ } - if (r300->state.stencil.hw_stencil) { -+ if (r300->radeon.state.stencil.hwBuffer) { ++ if (hw_stencil) { R300_STATECHANGE(r300, zs); if (state) { r300->hw.zs.cmd[R300_ZS_CNTL_0] |= -@@ -940,10 +938,9 @@ static void r300UpdateWindow(GLcontext * ctx) +@@ -935,15 +939,25 @@ static void r300UpdateWindow(GLcontext * ctx) + GLfloat xoffset = dPriv ? (GLfloat) dPriv->x : 0; + GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0; + const GLfloat *v = ctx->Viewport._WindowMap.m; ++ const GLfloat depthScale = 1.0F / ctx->DrawBuffer->_DepthMaxF; ++ const GLboolean render_to_fbo = (ctx->DrawBuffer->Name != 0); ++ GLfloat y_scale, y_bias; ++ ++ if (render_to_fbo) { ++ y_scale = 1.0; ++ y_bias = 0; ++ } else { ++ y_scale = -1.0; ++ y_bias = yoffset; ++ } + + GLfloat sx = v[MAT_SX]; GLfloat tx = v[MAT_TX] + xoffset + SUBPIXEL_X; - GLfloat sy = -v[MAT_SY]; - GLfloat ty = (-v[MAT_TY]) + yoffset + SUBPIXEL_Y; +- GLfloat sy = -v[MAT_SY]; +- GLfloat ty = (-v[MAT_TY]) + yoffset + SUBPIXEL_Y; - GLfloat sz = v[MAT_SZ] * rmesa->state.depth.scale; - GLfloat tz = v[MAT_TZ] * rmesa->state.depth.scale; -+ GLfloat sz = v[MAT_SZ] * rmesa->radeon.state.depth.scale; -+ GLfloat tz = v[MAT_TZ] * rmesa->radeon.state.depth.scale; ++ GLfloat sy = v[MAT_SY] * y_scale; ++ GLfloat ty = (v[MAT_TY] * y_scale) + y_bias + SUBPIXEL_Y; ++ GLfloat sz = v[MAT_SZ] * depthScale; ++ GLfloat tz = v[MAT_TZ] * depthScale; - R300_FIREVERTICES(rmesa); R300_STATECHANGE(rmesa, vpt); rmesa->hw.vpt.cmd[R300_VPT_XSCALE] = r300PackFloat32(sx); -@@ -962,6 +959,8 @@ static void r300Viewport(GLcontext * ctx, GLint x, GLint y, +@@ -962,6 +976,8 @@ static void r300Viewport(GLcontext * ctx, GLint x, GLint y, * values, or keep the originals hanging around. */ r300UpdateWindow(ctx); @@ -14100,7 +14114,7 @@ index 8095538..f423029 100644 } static void r300DepthRange(GLcontext * ctx, GLclampd nearval, GLclampd farval) -@@ -994,64 +993,6 @@ void r300UpdateViewportOffset(GLcontext * ctx) +@@ -994,64 +1010,6 @@ void r300UpdateViewportOffset(GLcontext * ctx) radeonUpdateScissor(ctx); } @@ -14165,7 +14179,7 @@ index 8095538..f423029 100644 static void r300FetchStateParameter(GLcontext * ctx, const gl_state_index state[STATE_LENGTH], -@@ -1269,7 +1210,8 @@ static void r300SetupFragmentShaderTextures(GLcontext *ctx, int *tmu_mappings) +@@ -1269,7 +1227,8 @@ static void r300SetupFragmentShaderTextures(GLcontext *ctx, int *tmu_mappings) } r300->hw.fpt.cmd[R300_FPT_CMD_0] = @@ -14175,7 +14189,7 @@ index 8095538..f423029 100644 } static void r500SetupFragmentShaderTextures(GLcontext *ctx, int *tmu_mappings) -@@ -1320,7 +1262,7 @@ static GLuint translate_lod_bias(GLfloat bias) +@@ -1320,7 +1279,7 @@ static GLuint translate_lod_bias(GLfloat bias) static void r300SetupTextures(GLcontext * ctx) { int i, mtu; @@ -14184,7 +14198,7 @@ index 8095538..f423029 100644 r300ContextPtr r300 = R300_CONTEXT(ctx); int hw_tmu = 0; int last_hw_tmu = -1; /* -1 translates into no setup costs for fields */ -@@ -1354,21 +1296,16 @@ static void r300SetupTextures(GLcontext * ctx) +@@ -1354,21 +1313,16 @@ static void r300SetupTextures(GLcontext * ctx) /* We cannot let disabled tmu offsets pass DRM */ for (i = 0; i < mtu; i++) { if (ctx->Texture.Unit[i]._ReallyEnabled) { @@ -14209,7 +14223,7 @@ index 8095538..f423029 100644 } if (RADEON_DEBUG & DEBUG_STATE) -@@ -1379,29 +1316,28 @@ static void r300SetupTextures(GLcontext * ctx) +@@ -1379,29 +1333,28 @@ static void r300SetupTextures(GLcontext * ctx) r300->hw.tex.filter.cmd[R300_TEX_VALUE_0 + hw_tmu] = @@ -14248,7 +14262,7 @@ index 8095538..f423029 100644 WARN_ONCE("micro tiling enabled!\n"); } -@@ -1418,21 +1354,21 @@ static void r300SetupTextures(GLcontext * ctx) +@@ -1418,21 +1371,21 @@ static void r300SetupTextures(GLcontext * ctx) } r300->hw.tex.filter.cmd[R300_TEX_CMD_0] = @@ -14278,7 +14292,7 @@ index 8095538..f423029 100644 if (!fp) /* should only happenen once, just after context is created */ return; -@@ -1444,7 +1380,7 @@ static void r300SetupTextures(GLcontext * ctx) +@@ -1444,7 +1397,7 @@ static void r300SetupTextures(GLcontext * ctx) r300->hw.txe.cmd[R300_TXE_ENABLE] |= 1; r300->hw.tex.filter.cmd[R300_TEX_VALUE_0] = 0; r300->hw.tex.filter.cmd[R300_TEX_CMD_0] = @@ -14287,7 +14301,7 @@ index 8095538..f423029 100644 } r300SetupFragmentShaderTextures(ctx, tmu_mappings); } else -@@ -1609,7 +1545,7 @@ static void r300SetupRSUnit(GLcontext * ctx) +@@ -1609,7 +1562,7 @@ static void r300SetupRSUnit(GLcontext * ctx) r300->hw.rc.cmd[1] |= (rs_tex_count << R300_IT_COUNT_SHIFT) | (col_ip << R300_IC_COUNT_SHIFT) | R300_HIRES_EN; r300->hw.rc.cmd[2] |= high_rr - 1; @@ -14296,7 +14310,7 @@ index 8095538..f423029 100644 if (InputsRead) WARN_ONCE("Don't know how to satisfy InputsRead=0x%08x\n", InputsRead); -@@ -1787,7 +1723,7 @@ static void r500SetupRSUnit(GLcontext * ctx) +@@ -1787,7 +1740,7 @@ static void r500SetupRSUnit(GLcontext * ctx) r300->hw.rc.cmd[1] |= (rs_tex_count << R300_IT_COUNT_SHIFT) | (col_ip << R300_IC_COUNT_SHIFT) | R300_HIRES_EN; r300->hw.rc.cmd[2] |= 0xC0 | (high_rr - 1); @@ -14305,7 +14319,7 @@ index 8095538..f423029 100644 if (InputsRead) WARN_ONCE("Don't know how to satisfy InputsRead=0x%08x\n", InputsRead); -@@ -1984,6 +1920,7 @@ static void r300SetupRealVertexProgram(r300ContextPtr rmesa) +@@ -1984,6 +1937,7 @@ static void r300SetupRealVertexProgram(r300ContextPtr rmesa) (inst_count << R300_PVS_LAST_VTX_SRC_INST_SHIFT); } @@ -14313,7 +14327,7 @@ index 8095538..f423029 100644 static void r300SetupVertexProgram(r300ContextPtr rmesa) { GLcontext *ctx = rmesa->radeon.glCtx; -@@ -2013,6 +1950,7 @@ static void r300SetupVertexProgram(r300ContextPtr rmesa) +@@ -2013,6 +1967,7 @@ static void r300SetupVertexProgram(r300ContextPtr rmesa) */ static void r300Enable(GLcontext * ctx, GLenum cap, GLboolean state) { @@ -14321,7 +14335,7 @@ index 8095538..f423029 100644 if (RADEON_DEBUG & DEBUG_STATE) fprintf(stderr, "%s( %s = %s )\n", __FUNCTION__, _mesa_lookup_enum_by_nr(cap), -@@ -2058,8 +1996,12 @@ static void r300Enable(GLcontext * ctx, GLenum cap, GLboolean state) +@@ -2058,8 +2013,12 @@ static void r300Enable(GLcontext * ctx, GLenum cap, GLboolean state) case GL_POLYGON_OFFSET_FILL: r300SetPolygonOffsetState(ctx, state); break; @@ -14335,7 +14349,7 @@ index 8095538..f423029 100644 break; } } -@@ -2070,6 +2012,7 @@ static void r300Enable(GLcontext * ctx, GLenum cap, GLboolean state) +@@ -2070,6 +2029,7 @@ static void r300Enable(GLcontext * ctx, GLenum cap, GLboolean state) static void r300ResetHwState(r300ContextPtr r300) { GLcontext *ctx = r300->radeon.glCtx; @@ -14343,15 +14357,17 @@ index 8095538..f423029 100644 int has_tcl = 1; if (!(r300->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) -@@ -2078,6 +2021,7 @@ static void r300ResetHwState(r300ContextPtr r300) +@@ -2078,7 +2038,8 @@ static void r300ResetHwState(r300ContextPtr r300) if (RADEON_DEBUG & DEBUG_STATE) fprintf(stderr, "%s\n", __FUNCTION__); +- r300UpdateWindow(ctx); + radeon_firevertices(&r300->radeon); - r300UpdateWindow(ctx); ++ //r300UpdateWindow(ctx); r300ColorMask(ctx, -@@ -2100,8 +2044,6 @@ static void r300ResetHwState(r300ContextPtr r300) + ctx->Color.ColorMask[RCOMP], +@@ -2100,8 +2061,6 @@ static void r300ResetHwState(r300ContextPtr r300) r300UpdateCulling(ctx); @@ -14360,7 +14376,7 @@ index 8095538..f423029 100644 r300SetBlendState(ctx); r300SetLogicOpState(ctx); -@@ -2240,20 +2182,6 @@ static void r300ResetHwState(r300ContextPtr r300) +@@ -2240,20 +2199,6 @@ static void r300ResetHwState(r300ContextPtr r300) r300BlendColor(ctx, ctx->Color.BlendColor); @@ -14381,7 +14397,7 @@ index 8095538..f423029 100644 r300->hw.rb3d_dither_ctl.cmd[1] = 0; r300->hw.rb3d_dither_ctl.cmd[2] = 0; r300->hw.rb3d_dither_ctl.cmd[3] = 0; -@@ -2269,12 +2197,8 @@ static void r300ResetHwState(r300ContextPtr r300) +@@ -2269,34 +2214,8 @@ static void r300ResetHwState(r300ContextPtr r300) r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[1] = 0x00000000; r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[2] = 0xffffffff; @@ -14391,13 +14407,14 @@ index 8095538..f423029 100644 - r300->hw.zb.cmd[R300_ZB_PITCH] = r300->radeon.radeonScreen->depthPitch; - - if (r300->radeon.sarea->tiling_enabled) { -+ rrb = r300->radeon.state.depth.rrb; -+ if (rrb && rrb->bo && (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)) { - /* XXX: Turn off when clearing buffers ? */ - r300->hw.zb.cmd[R300_ZB_PITCH] |= R300_DEPTHMACROTILE_ENABLE; - -@@ -2285,18 +2209,6 @@ static void r300ResetHwState(r300ContextPtr r300) - +- /* XXX: Turn off when clearing buffers ? */ +- r300->hw.zb.cmd[R300_ZB_PITCH] |= R300_DEPTHMACROTILE_ENABLE; +- +- if (ctx->Visual.depthBits == 24) +- r300->hw.zb.cmd[R300_ZB_PITCH] |= +- R300_DEPTHMICROTILE_TILED; +- } +- r300->hw.zb_depthclearvalue.cmd[1] = 0; - switch (ctx->Visual.depthBits) { @@ -14415,7 +14432,7 @@ index 8095538..f423029 100644 r300->hw.zstencil_format.cmd[2] = R300_ZTOP_DISABLE; r300->hw.zstencil_format.cmd[3] = 0x00000003; r300->hw.zstencil_format.cmd[4] = 0x00000000; -@@ -2317,7 +2229,7 @@ static void r300ResetHwState(r300ContextPtr r300) +@@ -2317,7 +2236,7 @@ static void r300ResetHwState(r300ContextPtr r300) r300->hw.vps.cmd[R300_VPS_ZERO_3] = 0; } @@ -14424,7 +14441,7 @@ index 8095538..f423029 100644 } void r300UpdateShaders(r300ContextPtr rmesa) -@@ -2328,8 +2240,8 @@ void r300UpdateShaders(r300ContextPtr rmesa) +@@ -2328,8 +2247,8 @@ void r300UpdateShaders(r300ContextPtr rmesa) ctx = rmesa->radeon.glCtx; @@ -14435,7 +14452,7 @@ index 8095538..f423029 100644 for (i = _TNL_FIRST_MAT; i <= _TNL_LAST_MAT; i++) { rmesa->temp_attrib[i] = -@@ -2408,10 +2320,10 @@ static void r300SetupPixelShader(r300ContextPtr rmesa) +@@ -2408,10 +2327,10 @@ static void r300SetupPixelShader(r300ContextPtr rmesa) R300_STATECHANGE(rmesa, fpi[1]); R300_STATECHANGE(rmesa, fpi[2]); R300_STATECHANGE(rmesa, fpi[3]); @@ -14450,7 +14467,7 @@ index 8095538..f423029 100644 for (i = 0; i < code->alu.length; i++) { rmesa->hw.fpi[0].cmd[R300_FPI_INSTR_0 + i] = code->alu.inst[i].inst0; rmesa->hw.fpi[1].cmd[R300_FPI_INSTR_0 + i] = code->alu.inst[i].inst1; -@@ -2442,7 +2354,7 @@ static void r300SetupPixelShader(r300ContextPtr rmesa) +@@ -2442,7 +2361,7 @@ static void r300SetupPixelShader(r300ContextPtr rmesa) } R300_STATECHANGE(rmesa, fpp); @@ -14459,7 +14476,7 @@ index 8095538..f423029 100644 for (i = 0; i < code->const_nr; i++) { const GLfloat *constant = get_fragmentprogram_constant(ctx, &fp->mesa_program.Base, code->constant[i]); -@@ -2534,7 +2446,6 @@ void r300UpdateShaderStates(r300ContextPtr rmesa) +@@ -2534,7 +2453,6 @@ void r300UpdateShaderStates(r300ContextPtr rmesa) GLcontext *ctx; ctx = rmesa->radeon.glCtx; @@ -14467,7 +14484,7 @@ index 8095538..f423029 100644 r300SetEarlyZState(ctx); /* w_fmt value is set to get best performance -@@ -2587,12 +2498,16 @@ static void r300InvalidateState(GLcontext * ctx, GLuint new_state) +@@ -2587,12 +2505,16 @@ static void r300InvalidateState(GLcontext * ctx, GLuint new_state) _ae_invalidate_state(ctx, new_state); if (new_state & (_NEW_BUFFERS | _NEW_COLOR | _NEW_PIXEL)) { @@ -14486,7 +14503,7 @@ index 8095538..f423029 100644 } /** -@@ -2605,26 +2520,9 @@ void r300InitState(r300ContextPtr r300) +@@ -2605,27 +2527,6 @@ void r300InitState(r300ContextPtr r300) GLcontext *ctx = r300->radeon.glCtx; GLuint depth_fmt; @@ -14507,15 +14524,14 @@ index 8095538..f423029 100644 - _mesa_exit(-1); - } - - /* Only have hw stencil when depth buffer is 24 bits deep */ +- /* Only have hw stencil when depth buffer is 24 bits deep */ - r300->state.stencil.hw_stencil = (ctx->Visual.stencilBits > 0 && - ctx->Visual.depthBits == 24); -+ r300->radeon.state.stencil.hwBuffer = (ctx->Visual.stencilBits > 0 && -+ ctx->Visual.depthBits == 24); - +- memset(&(r300->state.texture), 0, sizeof(r300->state.texture)); -@@ -2661,7 +2559,6 @@ void r300UpdateClipPlanes( GLcontext *ctx ) + r300ResetHwState(r300); +@@ -2661,7 +2562,6 @@ void r300UpdateClipPlanes( GLcontext *ctx ) */ void r300InitStateFuncs(struct dd_function_table *functions) { @@ -14523,7 +14539,7 @@ index 8095538..f423029 100644 functions->UpdateState = r300InvalidateState; functions->AlphaFunc = r300AlphaFunc; -@@ -2697,4 +2594,8 @@ void r300InitStateFuncs(struct dd_function_table *functions) +@@ -2697,4 +2597,8 @@ void r300InitStateFuncs(struct dd_function_table *functions) functions->RenderMode = r300RenderMode; functions->ClipPlane = r300ClipPlane; @@ -18438,7 +18454,7 @@ index 4f47afd..0000000 -} diff --git a/src/mesa/drivers/dri/r300/radeon_lock.h b/src/mesa/drivers/dri/r300/radeon_lock.h deleted file mode 100644 -index a344837..64bdf94 +index a344837..0000000 --- a/src/mesa/drivers/dri/r300/radeon_lock.h +++ /dev/null @@ -1,115 +0,0 @@ @@ -18557,6 +18573,14 @@ index a344837..64bdf94 - } while (0) - -#endif /* __RADEON_LOCK_H__ */ +diff --git a/src/mesa/drivers/dri/r300/radeon_lock.h b/src/mesa/drivers/dri/r300/radeon_lock.h +new file mode 120000 +index 0000000..64bdf94 +--- /dev/null ++++ b/src/mesa/drivers/dri/r300/radeon_lock.h +@@ -0,0 +1 @@ ++../radeon/radeon_lock.h +\ No newline at end of file diff --git a/src/mesa/drivers/dri/r300/radeon_program_pair.c b/src/mesa/drivers/dri/r300/radeon_program_pair.c index f398404..49aa90d 100644 --- a/src/mesa/drivers/dri/r300/radeon_program_pair.c @@ -20352,10 +20376,10 @@ index 0000000..9187cd7 +#endif diff --git a/src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h b/src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h new file mode 100644 -index 0000000..f80f0f7 +index 0000000..cb354c5 --- /dev/null +++ b/src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h -@@ -0,0 +1,67 @@ +@@ -0,0 +1,70 @@ +#ifndef RADEON_CS_WRAPPER_H +#define RADEON_CS_WRAPPER_H + @@ -20394,7 +20418,10 @@ index 0000000..f80f0f7 +#endif + + -+ ++static inline uint32_t radeon_gem_name_bo(struct radeon_bo *dummy) ++{ ++ return 0; ++} + +static inline void *radeon_bo_manager_gem_ctor(int fd) +{ @@ -20574,10 +20601,10 @@ index 0000000..4b5116c +#endif diff --git a/src/mesa/drivers/dri/radeon/radeon_common.c b/src/mesa/drivers/dri/radeon/radeon_common.c new file mode 100644 -index 0000000..840233f +index 0000000..9f646c4 --- /dev/null +++ b/src/mesa/drivers/dri/radeon/radeon_common.c -@@ -0,0 +1,1107 @@ +@@ -0,0 +1,1353 @@ +/************************************************************************** + +Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. @@ -20638,6 +20665,21 @@ index 0000000..840233f +#include "tnl/t_pipeline.h" +#include "swrast_setup/swrast_setup.h" + ++#include "main/blend.h" ++#include "main/bufferobj.h" ++#include "main/buffers.h" ++#include "main/depth.h" ++#include "main/shaders.h" ++#include "main/texstate.h" ++#include "main/varray.h" ++#include "glapi/dispatch.h" ++#include "swrast/swrast.h" ++#include "main/stencil.h" ++#include "main/matrix.h" ++#include "main/attrib.h" ++#include "main/enable.h" ++#include "main/viewport.h" ++ +#include "dri_util.h" +#include "vblank.h" + @@ -20712,10 +20754,10 @@ index 0000000..840233f + } +} + -+static void radeon_get_cliprects(radeonContextPtr radeon, -+ struct drm_clip_rect **cliprects, -+ unsigned int *num_cliprects, -+ int *x_off, int *y_off) ++void radeon_get_cliprects(radeonContextPtr radeon, ++ struct drm_clip_rect **cliprects, ++ unsigned int *num_cliprects, ++ int *x_off, int *y_off) +{ + __DRIdrawablePrivate *dPriv = radeon->dri.drawable; + struct radeon_framebuffer *rfb = dPriv->driverPrivate; @@ -21199,6 +21241,7 @@ index 0000000..840233f + radeonContextPtr radeon = RADEON_CONTEXT(ctx); + struct radeon_renderbuffer *rrbDepth = NULL, *rrbStencil = NULL, + *rrbColor = NULL; ++ uint32_t offset = 0; + + + if (!fb) { @@ -21237,17 +21280,20 @@ index 0000000..840233f + /* none */ + if (fb->Name == 0) { + if (fb->_ColorDrawBufferIndexes[0] == BUFFER_FRONT_LEFT) { -+ rrbColor = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; ++ rrbColor = radeon_renderbuffer(fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer); + radeon->front_cliprects = GL_TRUE; + } else { -+ rrbColor = (void *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; ++ rrbColor = radeon_renderbuffer(fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer); + radeon->front_cliprects = GL_FALSE; + } + } else { + /* user FBO in theory */ + struct radeon_renderbuffer *rrb; -+ rrb = (void *)fb->_ColorDrawBuffers[0]; -+ rrbColor = rrb; ++ rrb = radeon_renderbuffer(fb->_ColorDrawBuffers[0]); ++ if (rrb) { ++ offset = rrb->draw_offset; ++ rrbColor = rrb; ++ } + radeon->constant_cliprect = GL_TRUE; + } + @@ -21257,9 +21303,8 @@ index 0000000..840233f + radeon->vtbl.fallback(ctx, RADEON_FALLBACK_DRAW_BUFFER, GL_FALSE); + + -+ + if (fb->_DepthBuffer && fb->_DepthBuffer->Wrapped) { -+ rrbDepth = (struct radeon_renderbuffer *)fb->_DepthBuffer->Wrapped; ++ rrbDepth = radeon_renderbuffer(fb->_DepthBuffer->Wrapped); + if (rrbDepth && rrbDepth->bo) { + radeon->vtbl.fallback(ctx, RADEON_FALLBACK_DEPTH_BUFFER, GL_FALSE); + } else { @@ -21270,16 +21315,11 @@ index 0000000..840233f + rrbDepth = NULL; + } + -+ /* TODO stencil things */ + if (fb->_StencilBuffer && fb->_StencilBuffer->Wrapped) { -+ rrbStencil = (struct radeon_renderbuffer *)fb->_DepthBuffer->Wrapped; ++ rrbStencil = radeon_renderbuffer(fb->_DepthBuffer->Wrapped); + if (rrbStencil && rrbStencil->bo) { + radeon->vtbl.fallback(ctx, RADEON_FALLBACK_STENCIL_BUFFER, GL_FALSE); + /* need to re-compute stencil hw state */ -+ if (ctx->Driver.Enable != NULL) -+ ctx->Driver.Enable(ctx, GL_STENCIL_TEST, ctx->Stencil.Enabled); -+ else -+ ctx->NewState |= _NEW_STENCIL; + if (!rrbDepth) + rrbDepth = rrbStencil; + } else { @@ -21305,26 +21345,28 @@ index 0000000..840233f + * Update depth test state + */ + if (ctx->Driver.Enable) { -+ if (ctx->Depth.Test && fb->Visual.depthBits > 0) { -+ ctx->Driver.Enable(ctx, GL_DEPTH_TEST, GL_TRUE); -+ } else { -+ ctx->Driver.Enable(ctx, GL_DEPTH_TEST, GL_FALSE); -+ } ++ ctx->Driver.Enable(ctx, GL_DEPTH_TEST, ++ (ctx->Depth.Test && fb->Visual.depthBits > 0)); ++ ctx->Driver.Enable(ctx, GL_STENCIL_TEST, ++ (ctx->Stencil._Enabled && fb->Visual.stencilBits > 0)); + } else { -+ ctx->NewState |= _NEW_DEPTH; ++ ctx->NewState |= (_NEW_DEPTH | _NEW_STENCIL); + } + + radeon->state.depth.rrb = rrbDepth; -+ + radeon->state.color.rrb = rrbColor; ++ radeon->state.color.draw_offset = offset; + ++#if 0 + /* update viewport since it depends on window size */ + if (ctx->Driver.Viewport) { + ctx->Driver.Viewport(ctx, ctx->Viewport.X, ctx->Viewport.Y, + ctx->Viewport.Width, ctx->Viewport.Height); + } else { -+ ctx->NewState |= _NEW_VIEWPORT; ++ + } ++#endif ++ ctx->NewState |= _NEW_VIEWPORT; + + /* Set state we know depends on drawable parameters: + */ @@ -21332,6 +21374,19 @@ index 0000000..840233f + ctx->Driver.Scissor(ctx, ctx->Scissor.X, ctx->Scissor.Y, + ctx->Scissor.Width, ctx->Scissor.Height); + radeon->NewGLState |= _NEW_SCISSOR; ++ ++ if (ctx->Driver.DepthRange) ++ ctx->Driver.DepthRange(ctx, ++ ctx->Viewport.Near, ++ ctx->Viewport.Far); ++ ++ /* Update culling direction which changes depending on the ++ * orientation of the buffer: ++ */ ++ if (ctx->Driver.FrontFace) ++ ctx->Driver.FrontFace(ctx, ctx->Polygon.FrontFace); ++ else ++ ctx->NewState |= _NEW_POLYGON; +} + +/** @@ -21379,10 +21434,6 @@ index 0000000..840233f + +void radeon_window_moved(radeonContextPtr radeon) +{ -+ GLcontext *ctx = radeon->glCtx; -+ __DRIdrawablePrivate *dPriv = radeon->dri.drawable; -+ struct radeon_framebuffer *rfb = dPriv->driverPrivate; -+ + if (!radeon->radeonScreen->driScreen->dri2.enabled) { + radeonUpdatePageFlipping(radeon); + } @@ -21526,8 +21577,14 @@ index 0000000..840233f + if (radeon->radeonScreen->kernel_mm) { + for (i = 0; i < fb->_NumColorDrawBuffers; i++) { + struct radeon_renderbuffer *rrb; -+ rrb = (struct radeon_renderbuffer *)fb->_ColorDrawBuffers[i]; -+ if (rrb->bo) ++ rrb = radeon_renderbuffer(fb->_ColorDrawBuffers[i]); ++ if (rrb && rrb->bo) ++ radeon_bo_wait(rrb->bo); ++ } ++ { ++ struct radeon_renderbuffer *rrb; ++ rrb = radeon_get_depthbuffer(radeon); ++ if (rrb && rrb->bo) + radeon_bo_wait(rrb->bo); + } + } else if (radeon->do_irqs) { @@ -21685,12 +21742,228 @@ index 0000000..840233f + + + ++static void ++radeon_meta_set_passthrough_transform(radeonContextPtr radeon) ++{ ++ GLcontext *ctx = radeon->glCtx; ++ ++ radeon->meta.saved_vp_x = ctx->Viewport.X; ++ radeon->meta.saved_vp_y = ctx->Viewport.Y; ++ radeon->meta.saved_vp_width = ctx->Viewport.Width; ++ radeon->meta.saved_vp_height = ctx->Viewport.Height; ++ radeon->meta.saved_matrix_mode = ctx->Transform.MatrixMode; ++ ++ _mesa_Viewport(0, 0, ctx->DrawBuffer->Width, ctx->DrawBuffer->Height); ++ ++ _mesa_MatrixMode(GL_PROJECTION); ++ _mesa_PushMatrix(); ++ _mesa_LoadIdentity(); ++ _mesa_Ortho(0, ctx->DrawBuffer->Width, 0, ctx->DrawBuffer->Height, 1, -1); ++ ++ _mesa_MatrixMode(GL_MODELVIEW); ++ _mesa_PushMatrix(); ++ _mesa_LoadIdentity(); ++} ++ ++static void ++radeon_meta_restore_transform(radeonContextPtr radeon) ++{ ++ _mesa_MatrixMode(GL_PROJECTION); ++ _mesa_PopMatrix(); ++ _mesa_MatrixMode(GL_MODELVIEW); ++ _mesa_PopMatrix(); ++ ++ _mesa_MatrixMode(radeon->meta.saved_matrix_mode); ++ ++ _mesa_Viewport(radeon->meta.saved_vp_x, radeon->meta.saved_vp_y, ++ radeon->meta.saved_vp_width, radeon->meta.saved_vp_height); ++} ++ ++ ++/** ++ * Perform glClear where mask contains only color, depth, and/or stencil. ++ * ++ * The implementation is based on calling into Mesa to set GL state and ++ * performing normal triangle rendering. The intent of this path is to ++ * have as generic a path as possible, so that any driver could make use of ++ * it. ++ */ ++ ++ ++void radeon_clear_tris(GLcontext *ctx, GLbitfield mask) ++{ ++ radeonContextPtr rmesa = RADEON_CONTEXT(ctx); ++ GLfloat vertices[4][3]; ++ GLfloat color[4][4]; ++ GLfloat dst_z; ++ struct gl_framebuffer *fb = ctx->DrawBuffer; ++ int i; ++ GLboolean saved_fp_enable = GL_FALSE, saved_vp_enable = GL_FALSE; ++ GLboolean saved_shader_program = 0; ++ unsigned int saved_active_texture; ++ ++ assert((mask & ~(TRI_CLEAR_COLOR_BITS | BUFFER_BIT_DEPTH | ++ BUFFER_BIT_STENCIL)) == 0); ++ ++ _mesa_PushAttrib(GL_COLOR_BUFFER_BIT | ++ GL_CURRENT_BIT | ++ GL_DEPTH_BUFFER_BIT | ++ GL_ENABLE_BIT | ++ GL_STENCIL_BUFFER_BIT | ++ GL_TRANSFORM_BIT | ++ GL_CURRENT_BIT); ++ _mesa_PushClientAttrib(GL_CLIENT_VERTEX_ARRAY_BIT); ++ saved_active_texture = ctx->Texture.CurrentUnit; ++ ++ /* Disable existing GL state we don't want to apply to a clear. */ ++ _mesa_Disable(GL_ALPHA_TEST); ++ _mesa_Disable(GL_BLEND); ++ _mesa_Disable(GL_CULL_FACE); ++ _mesa_Disable(GL_FOG); ++ _mesa_Disable(GL_POLYGON_SMOOTH); ++ _mesa_Disable(GL_POLYGON_STIPPLE); ++ _mesa_Disable(GL_POLYGON_OFFSET_FILL); ++ _mesa_Disable(GL_LIGHTING); ++ _mesa_Disable(GL_CLIP_PLANE0); ++ _mesa_Disable(GL_CLIP_PLANE1); ++ _mesa_Disable(GL_CLIP_PLANE2); ++ _mesa_Disable(GL_CLIP_PLANE3); ++ _mesa_Disable(GL_CLIP_PLANE4); ++ _mesa_Disable(GL_CLIP_PLANE5); ++ if (ctx->Extensions.ARB_fragment_program && ctx->FragmentProgram.Enabled) { ++ saved_fp_enable = GL_TRUE; ++ _mesa_Disable(GL_FRAGMENT_PROGRAM_ARB); ++ } ++ if (ctx->Extensions.ARB_vertex_program && ctx->VertexProgram.Enabled) { ++ saved_vp_enable = GL_TRUE; ++ _mesa_Disable(GL_VERTEX_PROGRAM_ARB); ++ } ++ if (ctx->Extensions.ARB_shader_objects && ctx->Shader.CurrentProgram) { ++ saved_shader_program = ctx->Shader.CurrentProgram->Name; ++ _mesa_UseProgramObjectARB(0); ++ } ++ ++ if (ctx->Texture._EnabledUnits != 0) { ++ int i; ++ ++ for (i = 0; i < ctx->Const.MaxTextureUnits; i++) { ++ _mesa_ActiveTextureARB(GL_TEXTURE0 + i); ++ _mesa_Disable(GL_TEXTURE_1D); ++ _mesa_Disable(GL_TEXTURE_2D); ++ _mesa_Disable(GL_TEXTURE_3D); ++ if (ctx->Extensions.ARB_texture_cube_map) ++ _mesa_Disable(GL_TEXTURE_CUBE_MAP_ARB); ++ if (ctx->Extensions.NV_texture_rectangle) ++ _mesa_Disable(GL_TEXTURE_RECTANGLE_NV); ++ if (ctx->Extensions.MESA_texture_array) { ++ _mesa_Disable(GL_TEXTURE_1D_ARRAY_EXT); ++ _mesa_Disable(GL_TEXTURE_2D_ARRAY_EXT); ++ } ++ } ++ } ++ ++ radeon_meta_set_passthrough_transform(rmesa); ++ ++ for (i = 0; i < 4; i++) { ++ color[i][0] = ctx->Color.ClearColor[0]; ++ color[i][1] = ctx->Color.ClearColor[1]; ++ color[i][2] = ctx->Color.ClearColor[2]; ++ color[i][3] = ctx->Color.ClearColor[3]; ++ } ++ ++ /* convert clear Z from [0,1] to NDC coord in [-1,1] */ ++ ++ dst_z = -1.0 + 2.0 * ctx->Depth.Clear; ++ /* Prepare the vertices, which are the same regardless of which buffer we're ++ * drawing to. ++ */ ++ vertices[0][0] = fb->_Xmin; ++ vertices[0][1] = fb->_Ymin; ++ vertices[0][2] = dst_z; ++ vertices[1][0] = fb->_Xmax; ++ vertices[1][1] = fb->_Ymin; ++ vertices[1][2] = dst_z; ++ vertices[2][0] = fb->_Xmax; ++ vertices[2][1] = fb->_Ymax; ++ vertices[2][2] = dst_z; ++ vertices[3][0] = fb->_Xmin; ++ vertices[3][1] = fb->_Ymax; ++ vertices[3][2] = dst_z; ++ ++ _mesa_ColorPointer(4, GL_FLOAT, 4 * sizeof(GLfloat), &color); ++ _mesa_VertexPointer(3, GL_FLOAT, 3 * sizeof(GLfloat), &vertices); ++ _mesa_Enable(GL_COLOR_ARRAY); ++ _mesa_Enable(GL_VERTEX_ARRAY); ++ ++ while (mask != 0) { ++ GLuint this_mask = 0; ++ GLuint color_bit; ++ ++ color_bit = _mesa_ffs(mask & TRI_CLEAR_COLOR_BITS); ++ if (color_bit != 0) ++ this_mask |= (1 << (color_bit - 1)); ++ ++ /* Clear depth/stencil in the same pass as color. */ ++ this_mask |= (mask & (BUFFER_BIT_DEPTH | BUFFER_BIT_STENCIL)); ++ ++ /* Select the current color buffer and use the color write mask if ++ * we have one, otherwise don't write any color channels. ++ */ ++ if (this_mask & BUFFER_BIT_FRONT_LEFT) ++ _mesa_DrawBuffer(GL_FRONT_LEFT); ++ else if (this_mask & BUFFER_BIT_BACK_LEFT) ++ _mesa_DrawBuffer(GL_BACK_LEFT); ++ else if (color_bit != 0) ++ _mesa_DrawBuffer(GL_COLOR_ATTACHMENT0 + ++ (color_bit - BUFFER_COLOR0 - 1)); ++ else ++ _mesa_ColorMask(GL_FALSE, GL_FALSE, GL_FALSE, GL_FALSE); ++ ++ /* Control writing of the depth clear value to depth. */ ++ if (this_mask & BUFFER_BIT_DEPTH) { ++ _mesa_DepthFunc(GL_ALWAYS); ++ _mesa_DepthMask(GL_TRUE); ++ _mesa_Enable(GL_DEPTH_TEST); ++ } else { ++ _mesa_Disable(GL_DEPTH_TEST); ++ _mesa_DepthMask(GL_FALSE); ++ } ++ ++ /* Control writing of the stencil clear value to stencil. */ ++ if (this_mask & BUFFER_BIT_STENCIL) { ++ _mesa_Enable(GL_STENCIL_TEST); ++ _mesa_StencilOp(GL_REPLACE, GL_REPLACE, GL_REPLACE); ++ _mesa_StencilFuncSeparate(GL_FRONT, GL_ALWAYS, ctx->Stencil.Clear, ++ ctx->Stencil.WriteMask[0]); ++ } else { ++ _mesa_Disable(GL_STENCIL_TEST); ++ } ++ ++ CALL_DrawArrays(ctx->Exec, (GL_TRIANGLE_FAN, 0, 4)); ++ ++ mask &= ~this_mask; ++ } ++ ++ radeon_meta_restore_transform(rmesa); ++ ++ _mesa_ActiveTextureARB(GL_TEXTURE0 + saved_active_texture); ++ if (saved_fp_enable) ++ _mesa_Enable(GL_FRAGMENT_PROGRAM_ARB); ++ if (saved_vp_enable) ++ _mesa_Enable(GL_VERTEX_PROGRAM_ARB); ++ ++ if (saved_shader_program) ++ _mesa_UseProgramObjectARB(saved_shader_program); ++ ++ _mesa_PopClientAttrib(); ++ _mesa_PopAttrib(); ++} diff --git a/src/mesa/drivers/dri/radeon/radeon_common.h b/src/mesa/drivers/dri/radeon/radeon_common.h new file mode 100644 -index 0000000..814da1b +index 0000000..f3e2290 --- /dev/null +++ b/src/mesa/drivers/dri/radeon/radeon_common.h -@@ -0,0 +1,77 @@ +@@ -0,0 +1,97 @@ +#ifndef COMMON_MISC_H +#define COMMON_MISC_H + @@ -21698,6 +21971,18 @@ index 0000000..814da1b +#include "radeon_dma.h" +#include "radeon_texture.h" + ++ ++#define TRI_CLEAR_COLOR_BITS (BUFFER_BIT_BACK_LEFT | \ ++ BUFFER_BIT_FRONT_LEFT | \ ++ BUFFER_BIT_COLOR0 | \ ++ BUFFER_BIT_COLOR1 | \ ++ BUFFER_BIT_COLOR2 | \ ++ BUFFER_BIT_COLOR3 | \ ++ BUFFER_BIT_COLOR4 | \ ++ BUFFER_BIT_COLOR5 | \ ++ BUFFER_BIT_COLOR6 | \ ++ BUFFER_BIT_COLOR7) ++ +void radeonRecalcScissorRects(radeonContextPtr radeon); +void radeonSetCliprects(radeonContextPtr radeon); +void radeonUpdateScissor( GLcontext *ctx ); @@ -21717,12 +22002,24 @@ index 0000000..814da1b +void radeonFinish(GLcontext * ctx); +void radeonEmitState(radeonContextPtr radeon); + ++void radeon_clear_tris(GLcontext *ctx, GLbitfield mask); ++ +void radeon_window_moved(radeonContextPtr radeon); +void radeon_draw_buffer(GLcontext *ctx, struct gl_framebuffer *fb); +void radeonDrawBuffer( GLcontext *ctx, GLenum mode ); +void radeonReadBuffer( GLcontext *ctx, GLenum mode ); +void radeon_viewport(GLcontext *ctx, GLint x, GLint y, GLsizei width, GLsizei height); ++void radeon_get_cliprects(radeonContextPtr radeon, ++ struct drm_clip_rect **cliprects, ++ unsigned int *num_cliprects, ++ int *x_off, int *y_off); + ++void radeon_fbo_init(struct radeon_context *radeon); ++void ++radeon_renderbuffer_set_bo(struct radeon_renderbuffer *rb, ++ struct radeon_bo *bo); ++struct radeon_renderbuffer * ++radeon_create_renderbuffer(GLenum format, __DRIdrawablePrivate *driDrawPriv); +static inline struct radeon_renderbuffer *radeon_renderbuffer(struct gl_renderbuffer *rb) +{ + struct radeon_renderbuffer *rrb = (struct radeon_renderbuffer *)rb; @@ -21753,12 +22050,8 @@ index 0000000..814da1b +static inline struct radeon_renderbuffer *radeon_get_colorbuffer(radeonContextPtr rmesa) +{ + struct radeon_renderbuffer *rrb; -+ struct radeon_framebuffer *rfb = rmesa->dri.drawable->driverPrivate; + + rrb = rmesa->state.color.rrb; -+ if (rmesa->radeonScreen->driScreen->dri2.enabled) { -+ rrb = radeon_get_renderbuffer(&rfb->base, BUFFER_BACK_LEFT); -+ } + if (!rrb) + return NULL; + return rrb; @@ -21770,10 +22063,10 @@ index 0000000..814da1b +#endif diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.c b/src/mesa/drivers/dri/radeon/radeon_common_context.c new file mode 100644 -index 0000000..a818440 +index 0000000..5b23473 --- /dev/null +++ b/src/mesa/drivers/dri/radeon/radeon_common_context.c -@@ -0,0 +1,571 @@ +@@ -0,0 +1,602 @@ +/************************************************************************** + +Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and @@ -21939,6 +22232,12 @@ index 0000000..a818440 + "IRQ's not enabled, falling back to %s: %d %d\n", + radeon->do_usleeps ? "usleeps" : "busy waits", + fthrottle_mode, radeon->radeonScreen->irq); ++ ++ radeon->texture_depth = driQueryOptioni (&radeon->optionCache, ++ "texture_depth"); ++ if (radeon->texture_depth == DRI_CONF_TEXTURE_DEPTH_FB) ++ radeon->texture_depth = ( glVisual->rgbBits > 16 ) ? ++ DRI_CONF_TEXTURE_DEPTH_32 : DRI_CONF_TEXTURE_DEPTH_16; + + return GL_TRUE; +} @@ -22168,6 +22467,7 @@ index 0000000..a818440 + struct radeon_framebuffer *draw; + radeonContextPtr radeon; + char *regname; ++ struct radeon_bo *depth_bo, *bo; + + if (RADEON_DEBUG & DEBUG_DRI) + fprintf(stderr, "enter %s, drawable %p\n", __func__, drawable); @@ -22224,7 +22524,7 @@ index 0000000..a818440 + regname = "dri2 depth buffer"; + break; + case __DRI_BUFFER_STENCIL: -+ rb = radeon_get_renderbuffer(&draw->base, BUFFER_DEPTH); ++ rb = radeon_get_renderbuffer(&draw->base, BUFFER_STENCIL); + regname = "dri2 stencil buffer"; + break; + case __DRI_BUFFER_ACCUM: @@ -22239,25 +22539,49 @@ index 0000000..a818440 + continue; + + if (rb->bo) { -+ radeon_bo_unref(rb->bo); -+ rb->bo = NULL; ++ uint32_t name = radeon_gem_name_bo(rb->bo); ++ if (name == buffers[i].name) ++ continue; + } ++ ++ if (RADEON_DEBUG & DEBUG_DRI) ++ fprintf(stderr, ++ "attaching buffer %s, %d, at %d, cpp %d, pitch %d\n", ++ regname, buffers[i].name, buffers[i].attachment, ++ buffers[i].cpp, buffers[i].pitch); ++ + rb->cpp = buffers[i].cpp; + rb->pitch = buffers[i].pitch; + rb->width = drawable->w; + rb->height = drawable->h; + rb->has_surface = 0; -+ rb->bo = radeon_bo_open(radeon->radeonScreen->bom, -+ buffers[i].name, -+ 0, -+ 0, -+ RADEON_GEM_DOMAIN_VRAM, -+ buffers[i].flags); -+ if (rb->bo == NULL) { -+ fprintf(stderr, "failed to attach %s %d\n", -+ regname, buffers[i].name); + ++ if (buffers[i].attachment == __DRI_BUFFER_STENCIL && depth_bo) { ++ if (RADEON_DEBUG & DEBUG_DRI) ++ fprintf(stderr, "(reusing depth buffer as stencil)\n"); ++ bo = depth_bo; ++ radeon_bo_ref(bo); ++ } else { ++ bo = radeon_bo_open(radeon->radeonScreen->bom, ++ buffers[i].name, ++ 0, ++ 0, ++ RADEON_GEM_DOMAIN_VRAM, ++ buffers[i].flags); ++ if (bo == NULL) { ++ ++ fprintf(stderr, "failed to attach %s %d\n", ++ regname, buffers[i].name); ++ ++ } + } ++ ++ if (buffers[i].attachment == __DRI_BUFFER_DEPTH) ++ depth_bo = bo; ++ ++ radeon_renderbuffer_set_bo(rb, bo); ++ radeon_bo_unref(bo); ++ + } + + driUpdateFramebufferSize(radeon->glCtx, drawable); @@ -22347,10 +22671,10 @@ index 0000000..a818440 + diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.h b/src/mesa/drivers/dri/radeon/radeon_common_context.h new file mode 100644 -index 0000000..e5ada62 +index 0000000..0ce72c9 --- /dev/null +++ b/src/mesa/drivers/dri/radeon/radeon_common_context.h -@@ -0,0 +1,531 @@ +@@ -0,0 +1,545 @@ + +#ifndef COMMON_CONTEXT_H +#define COMMON_CONTEXT_H @@ -22435,6 +22759,7 @@ index 0000000..e5ada62 + unsigned int width; + unsigned int height; + ++ uint32_t draw_offset; /* FBO */ + /* boo Xorg 6.8.2 compat */ + int has_surface; + @@ -22470,11 +22795,11 @@ index 0000000..e5ada62 + GLuint clear; + int roundEnable; + struct radeon_renderbuffer *rrb; ++ uint32_t draw_offset; /* offset into color renderbuffer - FBOs */ +}; + +struct radeon_depthbuffer_state { + GLuint clear; -+ GLfloat scale; + struct radeon_renderbuffer *rrb; +}; + @@ -22488,7 +22813,6 @@ index 0000000..e5ada62 +}; + +struct radeon_stencilbuffer_state { -+ GLboolean hwBuffer; + GLuint clear; /* rb3d_stencilrefmask value */ +}; + @@ -22795,9 +23119,23 @@ index 0000000..e5ada62 + + struct radeon_cmdbuf cmdbuf; + -+ drm_clip_rect_t fboRect; -+ GLboolean constant_cliprect; /* use for FBO or DRI2 rendering */ -+ GLboolean front_cliprects; ++ drm_clip_rect_t fboRect; ++ GLboolean constant_cliprect; /* use for FBO or DRI2 rendering */ ++ GLboolean front_cliprects; ++ ++ struct { ++ struct gl_fragment_program *bitmap_fp; ++ struct gl_vertex_program *passthrough_vp; ++ ++ struct gl_fragment_program *saved_fp; ++ GLboolean saved_fp_enable; ++ struct gl_vertex_program *saved_vp; ++ GLboolean saved_vp_enable; ++ ++ GLint saved_vp_x, saved_vp_y; ++ GLsizei saved_vp_width, saved_vp_height; ++ GLenum saved_matrix_mode; ++ } meta; + + struct { + void (*get_lock)(radeonContextPtr radeon); @@ -23190,7 +23528,7 @@ index 46b490d..0000000 -} - diff --git a/src/mesa/drivers/dri/radeon/radeon_context.c b/src/mesa/drivers/dri/radeon/radeon_context.c -index ea81a32..47ebe41 100644 +index ea81a32..cad2c3e 100644 --- a/src/mesa/drivers/dri/radeon/radeon_context.c +++ b/src/mesa/drivers/dri/radeon/radeon_context.c @@ -53,6 +53,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. @@ -23201,7 +23539,15 @@ index ea81a32..47ebe41 100644 #include "radeon_context.h" #include "radeon_ioctl.h" #include "radeon_state.h" -@@ -72,40 +73,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +@@ -65,6 +66,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + #define need_GL_EXT_blend_minmax + #define need_GL_EXT_fog_coord + #define need_GL_EXT_secondary_color ++#define need_GL_EXT_framebuffer_object + #include "extension_helper.h" + + #define DRIVER_DATE "20061018" +@@ -72,40 +74,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "vblank.h" #include "utils.h" #include "xmlpool.h" /* for symbolic values of enum-type options */ @@ -23242,7 +23588,27 @@ index ea81a32..47ebe41 100644 /* Extension strings exported by the R100 driver. */ -@@ -160,15 +127,6 @@ static const struct tnl_pipeline_stage *radeon_pipeline[] = { +@@ -121,6 +89,7 @@ const struct dri_extension card_extensions[] = + { "GL_EXT_blend_logic_op", NULL }, + { "GL_EXT_blend_subtract", GL_EXT_blend_minmax_functions }, + { "GL_EXT_fog_coord", GL_EXT_fog_coord_functions }, ++ { "GL_EXT_packed_depth_stencil", NULL}, + { "GL_EXT_secondary_color", GL_EXT_secondary_color_functions }, + { "GL_EXT_stencil_wrap", NULL }, + { "GL_EXT_texture_edge_clamp", NULL }, +@@ -137,6 +106,11 @@ const struct dri_extension card_extensions[] = + { NULL, NULL } + }; + ++const struct dri_extension mm_extensions[] = { ++ { "GL_EXT_framebuffer_object", GL_EXT_framebuffer_object_functions }, ++ { NULL, NULL } ++}; ++ + extern const struct tnl_pipeline_stage _radeon_render_stage; + extern const struct tnl_pipeline_stage _radeon_tcl_stage; + +@@ -160,15 +134,6 @@ static const struct tnl_pipeline_stage *radeon_pipeline[] = { NULL, }; @@ -23258,7 +23624,7 @@ index ea81a32..47ebe41 100644 static const struct dri_debug_control debug_control[] = { { "fall", DEBUG_FALLBACKS }, -@@ -188,6 +146,51 @@ static const struct dri_debug_control debug_control[] = +@@ -188,6 +153,51 @@ static const struct dri_debug_control debug_control[] = { NULL, 0 } }; @@ -23310,7 +23676,7 @@ index ea81a32..47ebe41 100644 /* Create the device specific context. */ -@@ -199,8 +202,8 @@ radeonCreateContext( const __GLcontextModes *glVisual, +@@ -199,8 +209,8 @@ radeonCreateContext( const __GLcontextModes *glVisual, __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv; radeonScreenPtr screen = (radeonScreenPtr)(sPriv->private); struct dd_function_table functions; @@ -23321,7 +23687,7 @@ index ea81a32..47ebe41 100644 int i; int tcl_mode, fthrottle_mode; -@@ -209,10 +212,12 @@ radeonCreateContext( const __GLcontextModes *glVisual, +@@ -209,10 +219,12 @@ radeonCreateContext( const __GLcontextModes *glVisual, assert(screen); /* Allocate the Radeon context */ @@ -23335,7 +23701,7 @@ index ea81a32..47ebe41 100644 /* init exp fog table data */ radeonInitStaticFogData(); -@@ -220,12 +225,12 @@ radeonCreateContext( const __GLcontextModes *glVisual, +@@ -220,12 +232,12 @@ radeonCreateContext( const __GLcontextModes *glVisual, * Do this here so that initialMaxAnisotropy is set before we create * the default textures. */ @@ -23351,7 +23717,7 @@ index ea81a32..47ebe41 100644 if ( sPriv->drm_version.minor < 13 ) fprintf( stderr, "DRM version 1.%d too old to support HyperZ, " "disabling.\n", sPriv->drm_version.minor ); -@@ -240,65 +245,23 @@ radeonCreateContext( const __GLcontextModes *glVisual, +@@ -240,65 +252,17 @@ radeonCreateContext( const __GLcontextModes *glVisual, * (the texture functions are especially important) */ _mesa_init_driver_functions( &functions ); @@ -23368,7 +23734,12 @@ index ea81a32..47ebe41 100644 - if (!rmesa->glCtx) { - FREE(rmesa); - return GL_FALSE; -- } ++ if (!radeonInitContext(&rmesa->radeon, &functions, ++ glVisual, driContextPriv, ++ sharedContextPrivate)) { ++ FREE(rmesa); ++ return GL_FALSE; + } - driContextPriv->driverPrivate = rmesa; - - /* Init radeon context data */ @@ -23405,21 +23776,12 @@ index ea81a32..47ebe41 100644 - - driSetTextureSwapCounterLocation( rmesa->texture_heaps[i], - & rmesa->c_textureSwaps ); -+ if (!radeonInitContext(&rmesa->radeon, &functions, -+ glVisual, driContextPriv, -+ sharedContextPrivate)) { -+ FREE(rmesa); -+ return GL_FALSE; - } +- } - rmesa->texture_depth = driQueryOptioni (&rmesa->optionCache, -+ -+ rmesa->radeon.texture_depth = driQueryOptioni (&rmesa->radeon.optionCache, - "texture_depth"); +- "texture_depth"); - if (rmesa->texture_depth == DRI_CONF_TEXTURE_DEPTH_FB) - rmesa->texture_depth = ( screen->cpp == 4 ) ? -+ if (rmesa->radeon.texture_depth == DRI_CONF_TEXTURE_DEPTH_FB) -+ rmesa->radeon.texture_depth = ( screen->cpp == 4 ) ? - DRI_CONF_TEXTURE_DEPTH_32 : DRI_CONF_TEXTURE_DEPTH_16; +- DRI_CONF_TEXTURE_DEPTH_32 : DRI_CONF_TEXTURE_DEPTH_16; - rmesa->swtcl.RenderIndex = ~0; - rmesa->hw.all_dirty = GL_TRUE; @@ -23428,7 +23790,7 @@ index ea81a32..47ebe41 100644 /* Set the maximum texture size small enough that we can guarentee that * all texture units can bind a maximal texture and have all of them in -@@ -306,26 +269,13 @@ radeonCreateContext( const __GLcontextModes *glVisual, +@@ -306,26 +270,13 @@ radeonCreateContext( const __GLcontextModes *glVisual, * setting allow larger textures. */ @@ -23458,11 +23820,13 @@ index ea81a32..47ebe41 100644 ctx->Const.MaxTextureMaxAnisotropy = 16.0; -@@ -388,38 +338,36 @@ radeonCreateContext( const __GLcontextModes *glVisual, +@@ -388,38 +339,39 @@ radeonCreateContext( const __GLcontextModes *glVisual, } driInitExtensions( ctx, card_extensions, GL_TRUE ); - if (rmesa->radeonScreen->drmSupportsCubeMapsR100) ++ if (rmesa->radeon.radeonScreen->kernel_mm) ++ driInitExtensions(ctx, mm_extensions, GL_FALSE); + if (rmesa->radeon.radeonScreen->drmSupportsCubeMapsR100) _mesa_enable_extension( ctx, "GL_ARB_texture_cube_map" ); - if (rmesa->glCtx->Mesa_DXTn) { @@ -23480,6 +23844,7 @@ index ea81a32..47ebe41 100644 _mesa_enable_extension( ctx, "GL_NV_texture_rectangle"); /* XXX these should really go right after _mesa_init_driver_functions() */ ++ radeon_fbo_init(&rmesa->radeon); + radeonInitSpanFuncs( ctx ); radeonInitIoctlFuncs( ctx ); radeonInitStateFuncs( ctx ); @@ -23508,7 +23873,7 @@ index ea81a32..47ebe41 100644 #if DO_DEBUG -@@ -427,20 +375,20 @@ radeonCreateContext( const __GLcontextModes *glVisual, +@@ -427,20 +379,20 @@ radeonCreateContext( const __GLcontextModes *glVisual, debug_control ); #endif @@ -23536,7 +23901,7 @@ index ea81a32..47ebe41 100644 /* _tnl_need_dlist_norm_lengths( ctx, GL_FALSE ); */ } return GL_TRUE; -@@ -454,179 +402,41 @@ radeonCreateContext( const __GLcontextModes *glVisual, +@@ -454,179 +406,41 @@ radeonCreateContext( const __GLcontextModes *glVisual, void radeonDestroyContext( __DRIcontextPrivate *driContextPriv ) { GET_CURRENT_CONTEXT(ctx); @@ -23733,7 +24098,7 @@ index ea81a32..47ebe41 100644 - return GL_TRUE; -} diff --git a/src/mesa/drivers/dri/radeon/radeon_context.h b/src/mesa/drivers/dri/radeon/radeon_context.h -index 53df766..2015e96 100644 +index 53df766..5235a6e 100644 --- a/src/mesa/drivers/dri/radeon/radeon_context.h +++ b/src/mesa/drivers/dri/radeon/radeon_context.h @@ -48,91 +48,23 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. @@ -23798,12 +24163,12 @@ index 53df766..2015e96 100644 +#include "radeon_common.h" -typedef void (*radeon_point_func) (radeonContextPtr, radeonVertex *); - +- -struct radeon_colorbuffer_state { - GLuint clear; - int roundEnable; -}; -- + -struct radeon_depthbuffer_state { - GLuint clear; - GLfloat scale; @@ -24058,9 +24423,9 @@ index 53df766..2015e96 100644 - GLuint vertex_offset; - GLuint vertex_size; -}; - --#define RADEON_MAX_PRIMS 64 - +-#define RADEON_MAX_PRIMS 64 + -struct radeon_prim { - GLuint start; - GLuint end; @@ -24164,24 +24529,10 @@ index 53df766..2015e96 100644 GLboolean using_hyperz; GLboolean texmicrotile; -@@ -703,23 +434,26 @@ struct radeon_context { +@@ -703,23 +434,12 @@ struct radeon_context { GLuint c_textureSwaps; GLuint c_textureBytes; GLuint c_vertexBuffers; -+ -+ struct { -+ struct gl_fragment_program *bitmap_fp; -+ struct gl_vertex_program *passthrough_vp; -+ -+ struct gl_fragment_program *saved_fp; -+ GLboolean saved_fp_enable; -+ struct gl_vertex_program *saved_vp; -+ GLboolean saved_vp_enable; -+ -+ GLint saved_vp_x, saved_vp_y; -+ GLsizei saved_vp_width, saved_vp_height; -+ GLenum saved_matrix_mode; -+ } meta; + }; @@ -24206,7 +24557,7 @@ index 53df766..2015e96 100644 #define RADEON_OLD_PACKETS 1 -@@ -727,37 +461,11 @@ extern void radeonDestroyContext(__DRIcontextPrivate * driContextPriv); +@@ -727,37 +447,11 @@ extern void radeonDestroyContext(__DRIcontextPrivate * driContextPriv); extern GLboolean radeonCreateContext(const __GLcontextModes * glVisual, __DRIcontextPrivate * driContextPriv, void *sharedContextPrivate); @@ -25407,8 +25758,581 @@ index 0000000..cee3744 + +void *rcommonAllocDmaLowVerts(radeonContextPtr rmesa, int nverts, int vsize); +#endif +diff --git a/src/mesa/drivers/dri/radeon/radeon_fbo.c b/src/mesa/drivers/dri/radeon/radeon_fbo.c +new file mode 100644 +index 0000000..4094585 +--- /dev/null ++++ b/src/mesa/drivers/dri/radeon/radeon_fbo.c +@@ -0,0 +1,567 @@ ++/************************************************************************** ++ * ++ * Copyright 2008 Red Hat Inc. ++ * All Rights Reserved. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the ++ * "Software"), to deal in the Software without restriction, including ++ * without limitation the rights to use, copy, modify, merge, publish, ++ * distribute, sub license, and/or sell copies of the Software, and to ++ * permit persons to whom the Software is furnished to do so, subject to ++ * the following conditions: ++ * ++ * The above copyright notice and this permission notice (including the ++ * next paragraph) shall be included in all copies or substantial portions ++ * of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF ++ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ++ * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR ++ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, ++ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE ++ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ * ++ **************************************************************************/ ++ ++ ++#include "main/imports.h" ++#include "main/macros.h" ++#include "main/mtypes.h" ++#include "main/fbobject.h" ++#include "main/framebuffer.h" ++#include "main/renderbuffer.h" ++#include "main/context.h" ++#include "main/texformat.h" ++#include "main/texrender.h" ++ ++#include "radeon_common.h" ++#include "radeon_mipmap_tree.h" ++ ++#define FILE_DEBUG_FLAG DEBUG_TEXTURE ++#define DBG(...) do { \ ++ if (RADEON_DEBUG & FILE_DEBUG_FLAG) \ ++ _mesa_printf(__VA_ARGS__); \ ++} while(0) ++ ++static struct gl_framebuffer * ++radeon_new_framebuffer(GLcontext *ctx, GLuint name) ++{ ++ return _mesa_new_framebuffer(ctx, name); ++} ++ ++static void ++radeon_delete_renderbuffer(struct gl_renderbuffer *rb) ++{ ++ struct radeon_renderbuffer *rrb = radeon_renderbuffer(rb); ++ ++ ASSERT(rrb); ++ ++ if (rrb && rrb->bo) { ++ radeon_bo_unref(rrb->bo); ++ } ++ _mesa_free(rrb); ++} ++ ++static void * ++radeon_get_pointer(GLcontext *ctx, struct gl_renderbuffer *rb, ++ GLint x, GLint y) ++{ ++ return NULL; ++} ++ ++/** ++ * Called via glRenderbufferStorageEXT() to set the format and allocate ++ * storage for a user-created renderbuffer. ++ */ ++static GLboolean ++radeon_alloc_renderbuffer_storage(GLcontext * ctx, struct gl_renderbuffer *rb, ++ GLenum internalFormat, ++ GLuint width, GLuint height) ++{ ++ struct radeon_context *radeon = RADEON_CONTEXT(ctx); ++ struct radeon_renderbuffer *rrb = radeon_renderbuffer(rb); ++ GLboolean software_buffer = GL_FALSE; ++ int cpp; ++ ++ ASSERT(rb->Name != 0); ++ switch (internalFormat) { ++ case GL_R3_G3_B2: ++ case GL_RGB4: ++ case GL_RGB5: ++ rb->_ActualFormat = GL_RGB5; ++ rb->DataType = GL_UNSIGNED_BYTE; ++ rb->RedBits = 5; ++ rb->GreenBits = 6; ++ rb->BlueBits = 5; ++ cpp = 2; ++ break; ++ case GL_RGB: ++ case GL_RGB8: ++ case GL_RGB10: ++ case GL_RGB12: ++ case GL_RGB16: ++ rb->_ActualFormat = GL_RGB8; ++ rb->DataType = GL_UNSIGNED_BYTE; ++ rb->RedBits = 8; ++ rb->GreenBits = 8; ++ rb->BlueBits = 8; ++ rb->AlphaBits = 0; ++ cpp = 4; ++ break; ++ case GL_RGBA: ++ case GL_RGBA2: ++ case GL_RGBA4: ++ case GL_RGB5_A1: ++ case GL_RGBA8: ++ case GL_RGB10_A2: ++ case GL_RGBA12: ++ case GL_RGBA16: ++ rb->_ActualFormat = GL_RGBA8; ++ rb->DataType = GL_UNSIGNED_BYTE; ++ rb->RedBits = 8; ++ rb->GreenBits = 8; ++ rb->BlueBits = 8; ++ rb->AlphaBits = 8; ++ cpp = 4; ++ break; ++ case GL_STENCIL_INDEX: ++ case GL_STENCIL_INDEX1_EXT: ++ case GL_STENCIL_INDEX4_EXT: ++ case GL_STENCIL_INDEX8_EXT: ++ case GL_STENCIL_INDEX16_EXT: ++ /* alloc a depth+stencil buffer */ ++ rb->_ActualFormat = GL_DEPTH24_STENCIL8_EXT; ++ rb->DataType = GL_UNSIGNED_INT_24_8_EXT; ++ rb->StencilBits = 8; ++ cpp = 4; ++ break; ++ case GL_DEPTH_COMPONENT16: ++ rb->_ActualFormat = GL_DEPTH_COMPONENT16; ++ rb->DataType = GL_UNSIGNED_SHORT; ++ rb->DepthBits = 16; ++ cpp = 2; ++ break; ++ case GL_DEPTH_COMPONENT: ++ case GL_DEPTH_COMPONENT24: ++ case GL_DEPTH_COMPONENT32: ++ rb->_ActualFormat = GL_DEPTH24_STENCIL8_EXT; ++ rb->DataType = GL_UNSIGNED_INT_24_8_EXT; ++ rb->DepthBits = 24; ++ cpp = 4; ++ break; ++ case GL_DEPTH_STENCIL_EXT: ++ case GL_DEPTH24_STENCIL8_EXT: ++ rb->_ActualFormat = GL_DEPTH24_STENCIL8_EXT; ++ rb->DataType = GL_UNSIGNED_INT_24_8_EXT; ++ rb->DepthBits = 24; ++ rb->StencilBits = 8; ++ cpp = 4; ++ break; ++ default: ++ _mesa_problem(ctx, ++ "Unexpected format in intel_alloc_renderbuffer_storage"); ++ return GL_FALSE; ++ } ++ ++ radeonFlush(ctx); ++ ++ if (rrb->bo) ++ radeon_bo_unref(rrb->bo); ++ ++ ++ if (software_buffer) { ++ return _mesa_soft_renderbuffer_storage(ctx, rb, internalFormat, ++ width, height); ++ } ++ else { ++ uint32_t size = width * height * cpp; ++ uint32_t pitch = ((cpp * width + 63) & ~63) / cpp; ++ ++ fprintf(stderr,"Allocating %d x %d radeon RBO (pitch %d)\n", width, ++ height, pitch); ++ ++ rrb->pitch = pitch * cpp; ++ rrb->cpp = cpp; ++ rrb->bo = radeon_bo_open(radeon->radeonScreen->bom, ++ 0, ++ size, ++ 0, ++ RADEON_GEM_DOMAIN_VRAM, ++ 0); ++ rb->Width = width; ++ rb->Height = height; ++ return GL_TRUE; ++ } ++ ++} ++ ++ ++/** ++ * Called for each hardware renderbuffer when a _window_ is resized. ++ * Just update fields. ++ * Not used for user-created renderbuffers! ++ */ ++static GLboolean ++radeon_alloc_window_storage(GLcontext * ctx, struct gl_renderbuffer *rb, ++ GLenum internalFormat, GLuint width, GLuint height) ++{ ++ ASSERT(rb->Name == 0); ++ rb->Width = width; ++ rb->Height = height; ++ rb->_ActualFormat = internalFormat; ++ ++ return GL_TRUE; ++} ++ ++ ++static void ++radeon_resize_buffers(GLcontext *ctx, struct gl_framebuffer *fb, ++ GLuint width, GLuint height) ++{ ++ struct radeon_framebuffer *radeon_fb = (struct radeon_framebuffer*)fb; ++ int i; ++ ++ _mesa_resize_framebuffer(ctx, fb, width, height); ++ ++ fb->Initialized = GL_TRUE; /* XXX remove someday */ ++ ++ if (fb->Name != 0) { ++ return; ++ } ++ ++ /* Make sure all window system renderbuffers are up to date */ ++ for (i = 0; i < 2; i++) { ++ struct gl_renderbuffer *rb = &radeon_fb->color_rb[i]->base; ++ ++ /* only resize if size is changing */ ++ if (rb && (rb->Width != width || rb->Height != height)) { ++ rb->AllocStorage(ctx, rb, rb->InternalFormat, width, height); ++ } ++ } ++} ++ ++ ++/** Dummy function for gl_renderbuffer::AllocStorage() */ ++static GLboolean ++radeon_nop_alloc_storage(GLcontext * ctx, struct gl_renderbuffer *rb, ++ GLenum internalFormat, GLuint width, GLuint height) ++{ ++ _mesa_problem(ctx, "radeon_op_alloc_storage should never be called."); ++ return GL_FALSE; ++} ++ ++struct radeon_renderbuffer * ++radeon_create_renderbuffer(GLenum format, __DRIdrawablePrivate *driDrawPriv) ++{ ++ struct radeon_renderbuffer *rrb; ++ ++ rrb = CALLOC_STRUCT(radeon_renderbuffer); ++ if (!rrb) ++ return NULL; ++ ++ _mesa_init_renderbuffer(&rrb->base, 0); ++ rrb->base.ClassID = RADEON_RB_CLASS; ++ ++ /* XXX format junk */ ++ switch (format) { ++ case GL_RGB5: ++ rrb->base._ActualFormat = GL_RGB5; ++ rrb->base._BaseFormat = GL_RGBA; ++ rrb->base.RedBits = 5; ++ rrb->base.GreenBits = 6; ++ rrb->base.BlueBits = 5; ++ rrb->base.DataType = GL_UNSIGNED_BYTE; ++ break; ++ case GL_RGBA8: ++ rrb->base._ActualFormat = GL_RGBA8; ++ rrb->base._BaseFormat = GL_RGBA; ++ rrb->base.RedBits = 8; ++ rrb->base.GreenBits = 8; ++ rrb->base.BlueBits = 8; ++ rrb->base.AlphaBits = 8; ++ rrb->base.DataType = GL_UNSIGNED_BYTE; ++ break; ++ case GL_STENCIL_INDEX8_EXT: ++ rrb->base._ActualFormat = GL_STENCIL_INDEX8_EXT; ++ rrb->base._BaseFormat = GL_STENCIL_INDEX; ++ rrb->base.StencilBits = 8; ++ rrb->base.DataType = GL_UNSIGNED_BYTE; ++ break; ++ case GL_DEPTH_COMPONENT16: ++ rrb->base._ActualFormat = GL_DEPTH_COMPONENT16; ++ rrb->base._BaseFormat = GL_DEPTH_COMPONENT; ++ rrb->base.DepthBits = 16; ++ rrb->base.DataType = GL_UNSIGNED_SHORT; ++ break; ++ case GL_DEPTH_COMPONENT24: ++ rrb->base._ActualFormat = GL_DEPTH24_STENCIL8_EXT; ++ rrb->base._BaseFormat = GL_DEPTH_COMPONENT; ++ rrb->base.DepthBits = 24; ++ rrb->base.DataType = GL_UNSIGNED_INT; ++ break; ++ case GL_DEPTH24_STENCIL8_EXT: ++ rrb->base._ActualFormat = GL_DEPTH24_STENCIL8_EXT; ++ rrb->base._BaseFormat = GL_DEPTH_STENCIL_EXT; ++ rrb->base.DepthBits = 24; ++ rrb->base.StencilBits = 8; ++ rrb->base.DataType = GL_UNSIGNED_INT_24_8_EXT; ++ break; ++ default: ++ fprintf(stderr, "%s: Unknown format 0x%04x\n", __FUNCTION__, format); ++ _mesa_delete_renderbuffer(&rrb->base); ++ return NULL; ++ } ++ ++ rrb->dPriv = driDrawPriv; ++ rrb->base.InternalFormat = format; ++ ++ rrb->base.Delete = radeon_delete_renderbuffer; ++ rrb->base.AllocStorage = radeon_alloc_window_storage; ++ rrb->base.GetPointer = radeon_get_pointer; ++ ++ rrb->bo = NULL; ++ return rrb; ++} ++ ++static struct gl_renderbuffer * ++radeon_new_renderbuffer(GLcontext * ctx, GLuint name) ++{ ++ struct radeon_renderbuffer *rrb; ++ ++ rrb = CALLOC_STRUCT(radeon_renderbuffer); ++ if (!rrb) ++ return NULL; ++ ++ _mesa_init_renderbuffer(&rrb->base, name); ++ rrb->base.ClassID = RADEON_RB_CLASS; ++ ++ rrb->base.Delete = radeon_delete_renderbuffer; ++ rrb->base.AllocStorage = radeon_alloc_renderbuffer_storage; ++ rrb->base.GetPointer = radeon_get_pointer; ++ ++ return &rrb->base; ++} ++ ++static void ++radeon_bind_framebuffer(GLcontext * ctx, GLenum target, ++ struct gl_framebuffer *fb, struct gl_framebuffer *fbread) ++{ ++ if (target == GL_FRAMEBUFFER_EXT || target == GL_DRAW_FRAMEBUFFER_EXT) { ++ radeon_draw_buffer(ctx, fb); ++ } ++ else { ++ /* don't need to do anything if target == GL_READ_FRAMEBUFFER_EXT */ ++ } ++} ++ ++static void ++radeon_framebuffer_renderbuffer(GLcontext * ctx, ++ struct gl_framebuffer *fb, ++ GLenum attachment, struct gl_renderbuffer *rb) ++{ ++ ++ radeonFlush(ctx); ++ ++ _mesa_framebuffer_renderbuffer(ctx, fb, attachment, rb); ++ radeon_draw_buffer(ctx, fb); ++} ++ ++ ++static GLboolean ++radeon_update_wrapper(GLcontext *ctx, struct radeon_renderbuffer *rrb, ++ struct gl_texture_image *texImage) ++{ ++ if (texImage->TexFormat == &_mesa_texformat_argb8888) { ++ rrb->cpp = 4; ++ rrb->base._ActualFormat = GL_RGBA8; ++ rrb->base._BaseFormat = GL_RGBA; ++ rrb->base.DataType = GL_UNSIGNED_BYTE; ++ DBG("Render to RGBA8 texture OK\n"); ++ } ++ else if (texImage->TexFormat == &_mesa_texformat_rgb565) { ++ rrb->cpp = 2; ++ rrb->base._ActualFormat = GL_RGB5; ++ rrb->base._BaseFormat = GL_RGB; ++ rrb->base.DataType = GL_UNSIGNED_SHORT; ++ DBG("Render to RGB5 texture OK\n"); ++ } ++ else if (texImage->TexFormat == &_mesa_texformat_z16) { ++ rrb->cpp = 2; ++ rrb->base._ActualFormat = GL_DEPTH_COMPONENT16; ++ rrb->base._BaseFormat = GL_DEPTH_COMPONENT; ++ rrb->base.DataType = GL_UNSIGNED_SHORT; ++ DBG("Render to DEPTH16 texture OK\n"); ++ } ++ else if (texImage->TexFormat == &_mesa_texformat_s8_z24) { ++ rrb->cpp = 4; ++ rrb->base._ActualFormat = GL_DEPTH24_STENCIL8_EXT; ++ rrb->base._BaseFormat = GL_DEPTH_STENCIL_EXT; ++ rrb->base.DataType = GL_UNSIGNED_INT_24_8_EXT; ++ DBG("Render to DEPTH_STENCIL texture OK\n"); ++ } ++ else { ++ DBG("Render to texture BAD FORMAT %d\n", ++ texImage->TexFormat->MesaFormat); ++ return GL_FALSE; ++ } ++ ++ rrb->pitch = texImage->Width * rrb->cpp; ++ rrb->base.InternalFormat = rrb->base._ActualFormat; ++ rrb->base.Width = texImage->Width; ++ rrb->base.Height = texImage->Height; ++ rrb->base.RedBits = texImage->TexFormat->RedBits; ++ rrb->base.GreenBits = texImage->TexFormat->GreenBits; ++ rrb->base.BlueBits = texImage->TexFormat->BlueBits; ++ rrb->base.AlphaBits = texImage->TexFormat->AlphaBits; ++ rrb->base.DepthBits = texImage->TexFormat->DepthBits; ++ ++ rrb->base.Delete = radeon_delete_renderbuffer; ++ rrb->base.AllocStorage = radeon_nop_alloc_storage; ++ ++ return GL_TRUE; ++} ++ ++ ++static struct radeon_renderbuffer * ++radeon_wrap_texture(GLcontext * ctx, struct gl_texture_image *texImage) ++{ ++ const GLuint name = ~0; /* not significant, but distinct for debugging */ ++ struct radeon_renderbuffer *rrb; ++ ++ /* make an radeon_renderbuffer to wrap the texture image */ ++ rrb = CALLOC_STRUCT(radeon_renderbuffer); ++ if (!rrb) { ++ _mesa_error(ctx, GL_OUT_OF_MEMORY, "glFramebufferTexture"); ++ return NULL; ++ } ++ ++ _mesa_init_renderbuffer(&rrb->base, name); ++ rrb->base.ClassID = RADEON_RB_CLASS; ++ ++ if (!radeon_update_wrapper(ctx, rrb, texImage)) { ++ _mesa_free(rrb); ++ return NULL; ++ } ++ ++ return rrb; ++ ++} ++static void ++radeon_render_texture(GLcontext * ctx, ++ struct gl_framebuffer *fb, ++ struct gl_renderbuffer_attachment *att) ++{ ++ struct gl_texture_image *newImage ++ = att->Texture->Image[att->CubeMapFace][att->TextureLevel]; ++ struct radeon_renderbuffer *rrb = radeon_renderbuffer(att->Renderbuffer); ++ radeon_texture_image *radeon_image; ++ GLuint imageOffset; ++ ++ (void) fb; ++ ++ ASSERT(newImage); ++ ++ if (newImage->Border != 0) { ++ /* Fallback on drawing to a texture with a border, which won't have a ++ * miptree. ++ */ ++ _mesa_reference_renderbuffer(&att->Renderbuffer, NULL); ++ _mesa_render_texture(ctx, fb, att); ++ return; ++ } ++ else if (!rrb) { ++ rrb = radeon_wrap_texture(ctx, newImage); ++ if (rrb) { ++ /* bind the wrapper to the attachment point */ ++ _mesa_reference_renderbuffer(&att->Renderbuffer, &rrb->base); ++ } ++ else { ++ /* fallback to software rendering */ ++ _mesa_render_texture(ctx, fb, att); ++ return; ++ } ++ } ++ ++ if (!radeon_update_wrapper(ctx, rrb, newImage)) { ++ _mesa_reference_renderbuffer(&att->Renderbuffer, NULL); ++ _mesa_render_texture(ctx, fb, att); ++ return; ++ } ++ ++ DBG("Begin render texture tid %x tex=%u w=%d h=%d refcount=%d\n", ++ _glthread_GetID(), ++ att->Texture->Name, newImage->Width, newImage->Height, ++ rrb->base.RefCount); ++ ++ /* point the renderbufer's region to the texture image region */ ++ radeon_image = (radeon_texture_image *)newImage; ++ if (rrb->bo != radeon_image->mt->bo) { ++ if (rrb->bo) ++ radeon_bo_unref(rrb->bo); ++ rrb->bo = radeon_image->mt->bo; ++ radeon_bo_ref(rrb->bo); ++ } ++ ++ /* compute offset of the particular 2D image within the texture region */ ++ imageOffset = radeon_miptree_image_offset(radeon_image->mt, ++ att->CubeMapFace, ++ att->TextureLevel); ++ ++ if (att->Texture->Target == GL_TEXTURE_3D) { ++ const GLuint *offsets = radeon_miptree_depth_offsets(radeon_image->mt, ++ att->TextureLevel); ++ imageOffset += offsets[att->Zoffset]; ++ } ++ ++ /* store that offset in the region */ ++ rrb->draw_offset = imageOffset; ++ ++ /* update drawing region, etc */ ++ radeon_draw_buffer(ctx, fb); ++} ++ ++static void ++radeon_finish_render_texture(GLcontext * ctx, ++ struct gl_renderbuffer_attachment *att) ++{ ++ ++} ++static void ++radeon_validate_framebuffer(GLcontext *ctx, struct gl_framebuffer *fb) ++{ ++} ++ ++static void ++radeon_blit_framebuffer(GLcontext *ctx, ++ GLint srcX0, GLint srcY0, GLint srcX1, GLint srcY1, ++ GLint dstX0, GLint dstY0, GLint dstX1, GLint dstY1, ++ GLbitfield mask, GLenum filter) ++{ ++} ++ ++void radeon_fbo_init(struct radeon_context *radeon) ++{ ++ radeon->glCtx->Driver.NewFramebuffer = radeon_new_framebuffer; ++ radeon->glCtx->Driver.NewRenderbuffer = radeon_new_renderbuffer; ++ radeon->glCtx->Driver.BindFramebuffer = radeon_bind_framebuffer; ++ radeon->glCtx->Driver.FramebufferRenderbuffer = radeon_framebuffer_renderbuffer; ++ radeon->glCtx->Driver.RenderTexture = radeon_render_texture; ++ radeon->glCtx->Driver.FinishRenderTexture = radeon_finish_render_texture; ++ radeon->glCtx->Driver.ResizeBuffers = radeon_resize_buffers; ++ radeon->glCtx->Driver.ValidateFramebuffer = radeon_validate_framebuffer; ++ radeon->glCtx->Driver.BlitFramebuffer = radeon_blit_framebuffer; ++} ++ ++ ++void radeon_renderbuffer_set_bo(struct radeon_renderbuffer *rb, ++ struct radeon_bo *bo) ++{ ++ struct radeon_bo *old; ++ old = rb->bo; ++ rb->bo = bo; ++ radeon_bo_ref(bo); ++ if (old) ++ radeon_bo_unref(old); ++} diff --git a/src/mesa/drivers/dri/radeon/radeon_ioctl.c b/src/mesa/drivers/dri/radeon/radeon_ioctl.c -index 09acf6b..22584f4 100644 +index 09acf6b..f18aa1a 100644 --- a/src/mesa/drivers/dri/radeon/radeon_ioctl.c +++ b/src/mesa/drivers/dri/radeon/radeon_ioctl.c @@ -37,12 +37,27 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. @@ -25515,7 +26439,7 @@ index 09acf6b..22584f4 100644 /* ============================================================= * Kernel command buffer handling */ -@@ -134,965 +80,572 @@ static void radeonBackUpAndEmitLostStateLocked( radeonContextPtr rmesa ) +@@ -134,965 +80,360 @@ static void radeonBackUpAndEmitLostStateLocked( radeonContextPtr rmesa ) /* The state atoms will be emitted in the order they appear in the atom list, * so this step is important. */ @@ -25766,15 +26690,15 @@ index 09acf6b..22584f4 100644 - rmesa->store.cmd_used = (rmesa->store.cmd_used + 2) & ~2; - dwords = (rmesa->store.cmd_used - rmesa->store.elts_start) / 4; + nr = rmesa->tcl.elt_used; -+ -+#if RADEON_OLD_PACKETS + + #if RADEON_OLD_PACKETS +- cmd[1] |= (dwords - 3) << 16; + if (rmesa->radeon.radeonScreen->kernel_mm) { + dwords -= 2; + } +#endif - - #if RADEON_OLD_PACKETS -- cmd[1] |= (dwords - 3) << 16; ++ ++#if RADEON_OLD_PACKETS + cmd[1] |= (dwords + 3) << 16; cmd[5] |= nr << RADEON_CP_VC_CNTL_NUM_SHIFT; #else @@ -25992,6 +26916,12 @@ index 09acf6b..22584f4 100644 - cmd[2].i = (component[i]->aos_start + - offset * component[i]->aos_stride * 4); - cmd += 3; +- } +- else { +- cmd[0].i = ((component[i]->aos_stride << 8) | +- (component[i]->aos_size << 0)); +- cmd[1].i = (component[i]->aos_start + +- offset * component[i]->aos_stride * 4); + BEGIN_BATCH(sz+2+(nr * 2)); + OUT_BATCH_PACKET3(RADEON_CP_PACKET3_3D_LOAD_VBPNTR, sz - 1); + OUT_BATCH(nr); @@ -26018,12 +26948,6 @@ index 09acf6b..22584f4 100644 + RADEON_GEM_DOMAIN_GTT, + 0, 0); } -- else { -- cmd[0].i = ((component[i]->aos_stride << 8) | -- (component[i]->aos_size << 0)); -- cmd[1].i = (component[i]->aos_start + -- offset * component[i]->aos_stride * 4); -- } - } - - if (RADEON_DEBUG & DEBUG_VERTS) { @@ -26281,32 +27205,9 @@ index 09acf6b..22584f4 100644 + voffset = rmesa->tcl.aos[nr - 1].offset + + offset * 4 * rmesa->tcl.aos[nr - 1].stride; + OUT_BATCH(voffset); -+ } -+ for (i = 0; i + 1 < nr; i += 2) { -+ voffset = rmesa->tcl.aos[i + 0].offset + -+ offset * 4 * rmesa->tcl.aos[i + 0].stride; -+ radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, -+ rmesa->tcl.aos[i+0].bo, -+ RADEON_GEM_DOMAIN_GTT, -+ 0, 0); -+ voffset = rmesa->tcl.aos[i + 1].offset + -+ offset * 4 * rmesa->tcl.aos[i + 1].stride; -+ radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, -+ rmesa->tcl.aos[i+1].bo, -+ RADEON_GEM_DOMAIN_GTT, -+ 0, 0); -+ } -+ if (nr & 1) { -+ voffset = rmesa->tcl.aos[nr - 1].offset + -+ offset * 4 * rmesa->tcl.aos[nr - 1].stride; -+ radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, -+ rmesa->tcl.aos[nr-1].bo, -+ RADEON_GEM_DOMAIN_GTT, -+ 0, 0); } - } -+ END_BATCH(); - +- } +- - UNLOCK_HARDWARE(rmesa); - - if (RADEON_DEBUG & DEBUG_DMA) @@ -26323,9 +27224,8 @@ index 09acf6b..22584f4 100644 - rmesa->dma.current.ptr = 0; - - rmesa->c_vertexBuffers++; -+#endif - } - +-} +- -void radeonReleaseDmaRegion( radeonContextPtr rmesa, - struct radeon_dma_region *region, - const char *caller ) @@ -26335,17 +27235,13 @@ index 09acf6b..22584f4 100644 - - if (!region->buf) - return; -+/* ================================================================ -+ * Buffer clear -+ */ -+#define RADEON_MAX_CLEARS 256 - +- - if (rmesa->dma.flush) - rmesa->dma.flush( rmesa ); - +- - if (--region->buf->refcount == 0) { - drm_radeon_cmd_header_t *cmd; - +- - if (RADEON_DEBUG & (DEBUG_IOCTL|DEBUG_DMA)) - fprintf(stderr, "%s -- DISCARD BUF %d\n", __FUNCTION__, - region->buf->buf->idx); @@ -26369,36 +27265,23 @@ index 09acf6b..22584f4 100644 - struct radeon_dma_region *region, - int bytes, - int alignment ) -+static void -+r100_meta_set_passthrough_transform(r100ContextPtr r100) - { +-{ - if (RADEON_DEBUG & DEBUG_IOCTL) - fprintf(stderr, "%s %d\n", __FUNCTION__, bytes); - - if (rmesa->dma.flush) - rmesa->dma.flush( rmesa ); -+ GLcontext *ctx = r100->radeon.glCtx; - +- - if (region->buf) - radeonReleaseDmaRegion( rmesa, region, __FUNCTION__ ); -+ r100->meta.saved_vp_x = ctx->Viewport.X; -+ r100->meta.saved_vp_y = ctx->Viewport.Y; -+ r100->meta.saved_vp_width = ctx->Viewport.Width; -+ r100->meta.saved_vp_height = ctx->Viewport.Height; -+ r100->meta.saved_matrix_mode = ctx->Transform.MatrixMode; - +- - alignment--; - rmesa->dma.current.start = rmesa->dma.current.ptr = - (rmesa->dma.current.ptr + alignment) & ~alignment; -+ _mesa_Viewport(0, 0, ctx->DrawBuffer->Width, ctx->DrawBuffer->Height); - +- - if ( rmesa->dma.current.ptr + bytes > rmesa->dma.current.end ) - radeonRefillCurrentDmaRegion( rmesa ); -+ _mesa_MatrixMode(GL_PROJECTION); -+ _mesa_PushMatrix(); -+ _mesa_LoadIdentity(); -+ _mesa_Ortho(0, ctx->DrawBuffer->Width, 0, ctx->DrawBuffer->Height, 1, -1); - +- - region->start = rmesa->dma.current.start; - region->ptr = rmesa->dma.current.start; - region->end = rmesa->dma.current.start + bytes; @@ -26409,19 +27292,14 @@ index 09acf6b..22584f4 100644 - rmesa->dma.current.ptr += bytes; /* bug - if alignment > 7 */ - rmesa->dma.current.start = - rmesa->dma.current.ptr = (rmesa->dma.current.ptr + 0x7) & ~0x7; -+ _mesa_MatrixMode(GL_MODELVIEW); -+ _mesa_PushMatrix(); -+ _mesa_LoadIdentity(); - } - +-} +- -/* ================================================================ - * SwapBuffers with client-side throttling - */ - -static uint32_t radeonGetLastFrame (radeonContextPtr rmesa) -+static void -+r100_meta_restore_transform(r100ContextPtr r100) - { +-{ - drm_radeon_getparam_t gp; - int ret; - uint32_t frame; @@ -26435,15 +27313,10 @@ index 09acf6b..22584f4 100644 - fprintf( stderr, "%s: drm_radeon_getparam_t: %d\n", __FUNCTION__, ret ); - exit(1); - } -+ _mesa_MatrixMode(GL_PROJECTION); -+ _mesa_PopMatrix(); -+ _mesa_MatrixMode(GL_MODELVIEW); -+ _mesa_PopMatrix(); - +- - return frame; -} -+ _mesa_MatrixMode(r100->meta.saved_matrix_mode); - +- -static void radeonEmitIrqLocked( radeonContextPtr rmesa ) -{ - drm_radeon_irq_emit_t ie; @@ -26456,22 +27329,11 @@ index 09acf6b..22584f4 100644 - fprintf( stderr, "%s: drm_radeon_irq_emit_t: %d\n", __FUNCTION__, ret ); - exit(1); - } -+ _mesa_Viewport(r100->meta.saved_vp_x, r100->meta.saved_vp_y, -+ r100->meta.saved_vp_width, r100->meta.saved_vp_height); - } - +-} +- - -static void radeonWaitIrq( radeonContextPtr rmesa ) -+/** -+ * Perform glClear where mask contains only color, depth, and/or stencil. -+ * -+ * The implementation is based on calling into Mesa to set GL state and -+ * performing normal triangle rendering. The intent of this path is to -+ * have as generic a path as possible, so that any driver could make use of -+ * it. -+ */ -+static void radeon_clear_tris(GLcontext *ctx, GLbitfield mask) - { +-{ - int ret; - - do { @@ -26482,56 +27344,7 @@ index 09acf6b..22584f4 100644 - if ( ret ) { - fprintf( stderr, "%s: drmRadeonIrqWait: %d\n", __FUNCTION__, ret ); - exit(1); -+ r100ContextPtr rmesa = R100_CONTEXT(ctx); -+ GLfloat vertices[4][3]; -+ GLfloat color[4][4]; -+ GLfloat dst_z; -+ struct gl_framebuffer *fb = ctx->DrawBuffer; -+ int i; -+ GLboolean saved_fp_enable = GL_FALSE, saved_vp_enable = GL_FALSE; -+ GLboolean saved_shader_program = 0; -+ unsigned int saved_active_texture; -+ -+ assert((mask & ~(BUFFER_BIT_BACK_LEFT | BUFFER_BIT_FRONT_LEFT | -+ BUFFER_BIT_DEPTH | BUFFER_BIT_STENCIL)) == 0); -+ -+ _mesa_PushAttrib(GL_COLOR_BUFFER_BIT | -+ GL_CURRENT_BIT | -+ GL_DEPTH_BUFFER_BIT | -+ GL_ENABLE_BIT | -+ GL_STENCIL_BUFFER_BIT | -+ GL_TRANSFORM_BIT | -+ GL_CURRENT_BIT); -+ _mesa_PushClientAttrib(GL_CLIENT_VERTEX_ARRAY_BIT); -+ saved_active_texture = ctx->Texture.CurrentUnit; -+ -+ /* Disable existing GL state we don't want to apply to a clear. */ -+ _mesa_Disable(GL_ALPHA_TEST); -+ _mesa_Disable(GL_BLEND); -+ _mesa_Disable(GL_CULL_FACE); -+ _mesa_Disable(GL_FOG); -+ _mesa_Disable(GL_POLYGON_SMOOTH); -+ _mesa_Disable(GL_POLYGON_STIPPLE); -+ _mesa_Disable(GL_POLYGON_OFFSET_FILL); -+ _mesa_Disable(GL_LIGHTING); -+ _mesa_Disable(GL_CLIP_PLANE0); -+ _mesa_Disable(GL_CLIP_PLANE1); -+ _mesa_Disable(GL_CLIP_PLANE2); -+ _mesa_Disable(GL_CLIP_PLANE3); -+ _mesa_Disable(GL_CLIP_PLANE4); -+ _mesa_Disable(GL_CLIP_PLANE5); -+ if (ctx->Extensions.ARB_fragment_program && ctx->FragmentProgram.Enabled) { -+ saved_fp_enable = GL_TRUE; -+ _mesa_Disable(GL_FRAGMENT_PROGRAM_ARB); -+ } -+ if (ctx->Extensions.ARB_vertex_program && ctx->VertexProgram.Enabled) { -+ saved_vp_enable = GL_TRUE; -+ _mesa_Disable(GL_VERTEX_PROGRAM_ARB); -+ } -+ if (ctx->Extensions.ARB_shader_objects && ctx->Shader.CurrentProgram) { -+ saved_shader_program = ctx->Shader.CurrentProgram->Name; -+ _mesa_UseProgramObjectARB(0); - } +- } -} - - @@ -26549,23 +27362,7 @@ index 09acf6b..22584f4 100644 - UNLOCK_HARDWARE( rmesa ); - radeonWaitIrq( rmesa ); - LOCK_HARDWARE( rmesa ); -+ -+ if (ctx->Texture._EnabledUnits != 0) { -+ int i; -+ -+ for (i = 0; i < ctx->Const.MaxTextureUnits; i++) { -+ _mesa_ActiveTextureARB(GL_TEXTURE0 + i); -+ _mesa_Disable(GL_TEXTURE_1D); -+ _mesa_Disable(GL_TEXTURE_2D); -+ _mesa_Disable(GL_TEXTURE_3D); -+ if (ctx->Extensions.ARB_texture_cube_map) -+ _mesa_Disable(GL_TEXTURE_CUBE_MAP_ARB); -+ if (ctx->Extensions.NV_texture_rectangle) -+ _mesa_Disable(GL_TEXTURE_RECTANGLE_NV); -+ if (ctx->Extensions.MESA_texture_array) { -+ _mesa_Disable(GL_TEXTURE_1D_ARRAY_EXT); -+ _mesa_Disable(GL_TEXTURE_2D_ARRAY_EXT); - } +- } - rmesa->irqsEmitted = 10; - } - @@ -26580,8 +27377,8 @@ index 09acf6b..22584f4 100644 - if (rmesa->do_usleeps) - DO_USLEEP( 1 ); - LOCK_HARDWARE( rmesa ); - } - } +- } +- } -} - -/* Copy the back color buffer to the front color buffer. @@ -26603,27 +27400,14 @@ index 09acf6b..22584f4 100644 - - if ( RADEON_DEBUG & DEBUG_IOCTL ) { - fprintf( stderr, "\n%s( %p )\n\n", __FUNCTION__, (void *) rmesa->glCtx ); -+ -+ r100_meta_set_passthrough_transform(rmesa); -+ -+ for (i = 0; i < 4; i++) { -+ color[i][0] = ctx->Color.ClearColor[0]; -+ color[i][1] = ctx->Color.ClearColor[1]; -+ color[i][2] = ctx->Color.ClearColor[2]; -+ color[i][3] = ctx->Color.ClearColor[3]; - } - +- } +- - RADEON_FIREVERTICES( rmesa ); - LOCK_HARDWARE( rmesa ); - - /* Throttle the frame rate -- only allow one pending swap buffers - * request at a time. -+ /* convert clear Z from [0,1] to NDC coord in [-1,1] */ -+ dst_z = -1.0 + 2.0 * ctx->Depth.Clear; -+ -+ /* Prepare the vertices, which are the same regardless of which buffer we're -+ * drawing to. - */ +- */ - radeonWaitForFrameCompletion( rmesa ); - if (!rect) - { @@ -26658,54 +27442,22 @@ index 09acf6b..22584f4 100644 - if (b->x1 >= b->x2 || b->y1 >= b->y2) - continue; - } -+ vertices[0][0] = fb->_Xmin; -+ vertices[0][1] = fb->_Ymin; -+ vertices[0][2] = dst_z; -+ vertices[1][0] = fb->_Xmax; -+ vertices[1][1] = fb->_Ymin; -+ vertices[1][2] = dst_z; -+ vertices[2][0] = fb->_Xmax; -+ vertices[2][1] = fb->_Ymax; -+ vertices[2][2] = dst_z; -+ vertices[3][0] = fb->_Xmin; -+ vertices[3][1] = fb->_Ymax; -+ vertices[3][2] = dst_z; -+ -+ _mesa_ColorPointer(4, GL_FLOAT, 4 * sizeof(GLfloat), &color); -+ _mesa_VertexPointer(3, GL_FLOAT, 3 * sizeof(GLfloat), &vertices); -+ _mesa_Enable(GL_COLOR_ARRAY); -+ _mesa_Enable(GL_VERTEX_ARRAY); -+ -+ while (mask != 0) { -+ GLuint this_mask = 0; -+ -+ if (mask & BUFFER_BIT_BACK_LEFT) -+ this_mask = BUFFER_BIT_BACK_LEFT; -+ else if (mask & BUFFER_BIT_FRONT_LEFT) -+ this_mask = BUFFER_BIT_FRONT_LEFT; -+ -+ /* Clear depth/stencil in the same pass as color. */ -+ this_mask |= (mask & (BUFFER_BIT_DEPTH | BUFFER_BIT_STENCIL)); -+ -+ /* Select the current color buffer and use the color write mask if -+ * we have one, otherwise don't write any color channels. -+ */ -+ if (this_mask & BUFFER_BIT_FRONT_LEFT) -+ _mesa_DrawBuffer(GL_FRONT_LEFT); -+ else if (this_mask & BUFFER_BIT_BACK_LEFT) -+ _mesa_DrawBuffer(GL_BACK_LEFT); -+ else -+ _mesa_ColorMask(GL_FALSE, GL_FALSE, GL_FALSE, GL_FALSE); - +- - b++; - n++; -+ /* Control writing of the depth clear value to depth. */ -+ if (this_mask & BUFFER_BIT_DEPTH) { -+ _mesa_DepthFunc(GL_ALWAYS); -+ _mesa_Enable(GL_DEPTH_TEST); -+ } else { -+ _mesa_Disable(GL_DEPTH_TEST); -+ _mesa_DepthMask(GL_FALSE); ++ for (i = 0; i + 1 < nr; i += 2) { ++ voffset = rmesa->tcl.aos[i + 0].offset + ++ offset * 4 * rmesa->tcl.aos[i + 0].stride; ++ radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, ++ rmesa->tcl.aos[i+0].bo, ++ RADEON_GEM_DOMAIN_GTT, ++ 0, 0); ++ voffset = rmesa->tcl.aos[i + 1].offset + ++ offset * 4 * rmesa->tcl.aos[i + 1].stride; ++ radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, ++ rmesa->tcl.aos[i+1].bo, ++ RADEON_GEM_DOMAIN_GTT, ++ 0, 0); } - rmesa->sarea->nbox = n; - @@ -26713,22 +27465,22 @@ index 09acf6b..22584f4 100644 - continue; - - ret = drmCommandNone( rmesa->dri.fd, DRM_RADEON_SWAP ); - +- - if ( ret ) { - fprintf( stderr, "DRM_RADEON_SWAP_BUFFERS: return = %d\n", ret ); - UNLOCK_HARDWARE( rmesa ); - exit( 1 ); -+ /* Control writing of the stencil clear value to stencil. */ -+ if (this_mask & BUFFER_BIT_STENCIL) { -+ _mesa_Enable(GL_STENCIL_TEST); -+ _mesa_StencilOp(GL_REPLACE, GL_REPLACE, GL_REPLACE); -+ _mesa_StencilFuncSeparate(GL_FRONT, GL_ALWAYS, ctx->Stencil.Clear, -+ ctx->Stencil.WriteMask[0]); -+ } else { -+ _mesa_Disable(GL_STENCIL_TEST); ++ if (nr & 1) { ++ voffset = rmesa->tcl.aos[nr - 1].offset + ++ offset * 4 * rmesa->tcl.aos[nr - 1].stride; ++ radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, ++ rmesa->tcl.aos[nr-1].bo, ++ RADEON_GEM_DOMAIN_GTT, ++ 0, 0); } -- } -- + } ++ END_BATCH(); + - UNLOCK_HARDWARE( rmesa ); - if (!rect) - { @@ -26758,7 +27510,7 @@ index 09acf6b..22584f4 100644 - - rmesa = (radeonContextPtr) dPriv->driContextPriv->driverPrivate; - psp = dPriv->driScreenPriv; - +- - if ( RADEON_DEBUG & DEBUG_IOCTL ) { - fprintf(stderr, "%s: pfCurrentPage: %d\n", __FUNCTION__, - rmesa->sarea->pfCurrentPage); @@ -26776,8 +27528,7 @@ index 09acf6b..22584f4 100644 - b[0] = box[0]; - rmesa->sarea->nbox = 1; - } -+ CALL_DrawArrays(ctx->Exec, (GL_TRIANGLE_FAN, 0, 4)); - +- - /* Throttle the frame rate -- only allow a few pending swap buffers - * request at a time. - */ @@ -26787,20 +27538,13 @@ index 09acf6b..22584f4 100644 - if ( missed_target ) { - rmesa->swap_missed_count++; - (void) (*psp->systemTime->getUST)( & rmesa->swap_missed_ust ); -+ mask &= ~this_mask; - } +- } - LOCK_HARDWARE( rmesa ); - +- - ret = drmCommandNone( rmesa->dri.fd, DRM_RADEON_FLIP ); -+ r100_meta_restore_transform(rmesa); - +- - UNLOCK_HARDWARE( rmesa ); -+ _mesa_ActiveTextureARB(GL_TEXTURE0 + saved_active_texture); -+ if (saved_fp_enable) -+ _mesa_Enable(GL_FRAGMENT_PROGRAM_ARB); -+ if (saved_vp_enable) -+ _mesa_Enable(GL_VERTEX_PROGRAM_ARB); - +- - if ( ret ) { - fprintf( stderr, "DRM_RADEON_FLIP: return = %d\n", ret ); - exit( 1 ); @@ -26808,9 +27552,7 @@ index 09acf6b..22584f4 100644 - - rmesa->swap_count++; - (void) (*psp->systemTime->getUST)( & rmesa->swap_ust ); -+ if (saved_shader_program) -+ _mesa_UseProgramObjectARB(saved_shader_program); - +- - /* Get ready for drawing next frame. Update the renderbuffers' - * flippedOffset/Pitch fields so we draw into the right place. - */ @@ -26818,21 +27560,21 @@ index 09acf6b..22584f4 100644 - rmesa->sarea->pfCurrentPage); - - radeonUpdateDrawBuffer(rmesa->glCtx); -+ _mesa_PopClientAttrib(); -+ _mesa_PopAttrib(); ++#endif } +- + /* ================================================================ + * Buffer clear + */ + #define RADEON_MAX_CLEARS 256 + +-static void radeonClear( GLcontext *ctx, GLbitfield mask ) +static void radeonUserClear(GLcontext *ctx, GLuint mask) +{ + radeon_clear_tris(ctx, mask); +} - --/* ================================================================ -- * Buffer clear -- */ --#define RADEON_MAX_CLEARS 256 -- --static void radeonClear( GLcontext *ctx, GLbitfield mask ) ++ +static void radeonKernelClear(GLcontext *ctx, GLuint flags) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); @@ -26907,7 +27649,7 @@ index 09acf6b..22584f4 100644 /* compute region after locking: */ cx = ctx->DrawBuffer->_Xmin; -@@ -1112,7 +665,7 @@ static void radeonClear( GLcontext *ctx, GLbitfield mask ) +@@ -1112,7 +453,7 @@ static void radeonClear( GLcontext *ctx, GLbitfield mask ) gp.param = RADEON_PARAM_LAST_CLEAR; gp.value = (int *)&clear; @@ -26916,7 +27658,7 @@ index 09acf6b..22584f4 100644 DRM_RADEON_GETPARAM, &gp, sizeof(gp) ); if ( ret ) { -@@ -1124,20 +677,20 @@ static void radeonClear( GLcontext *ctx, GLbitfield mask ) +@@ -1124,20 +465,20 @@ static void radeonClear( GLcontext *ctx, GLbitfield mask ) break; } @@ -26942,7 +27684,7 @@ index 09acf6b..22584f4 100644 drm_radeon_clear_t clear; drm_radeon_clear_rect_t depth_boxes[RADEON_NR_SAREA_CLIPRECTS]; GLint n = 0; -@@ -1172,105 +725,108 @@ static void radeonClear( GLcontext *ctx, GLbitfield mask ) +@@ -1172,105 +513,107 @@ static void radeonClear( GLcontext *ctx, GLbitfield mask ) } } @@ -27016,17 +27758,11 @@ index 09acf6b..22584f4 100644 + GLuint flags = 0; + GLuint color_mask = 0; + GLuint orig_mask = mask; - ++ + if ( RADEON_DEBUG & DEBUG_IOCTL ) { + fprintf( stderr, "radeonClear\n"); + } --static void radeonWaitForIdle( radeonContextPtr rmesa ) --{ -- LOCK_HARDWARE(rmesa); -- radeonWaitForIdleLocked( rmesa ); -- UNLOCK_HARDWARE(rmesa); --} + { + LOCK_HARDWARE( &rmesa->radeon ); + UNLOCK_HARDWARE( &rmesa->radeon ); @@ -27036,45 +27772,54 @@ index 09acf6b..22584f4 100644 + + radeon_firevertices(&rmesa->radeon); +-static void radeonWaitForIdle( radeonContextPtr rmesa ) +-{ +- LOCK_HARDWARE(rmesa); +- radeonWaitForIdleLocked( rmesa ); +- UNLOCK_HARDWARE(rmesa); +-} + if ( mask & BUFFER_BIT_FRONT_LEFT ) { + flags |= RADEON_FRONT; + color_mask = rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK]; + mask &= ~BUFFER_BIT_FRONT_LEFT; + } --void radeonFlush( GLcontext *ctx ) --{ -- radeonContextPtr rmesa = RADEON_CONTEXT( ctx ); + if ( mask & BUFFER_BIT_BACK_LEFT ) { + flags |= RADEON_BACK; + color_mask = rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK]; + mask &= ~BUFFER_BIT_BACK_LEFT; + } -- if (RADEON_DEBUG & DEBUG_IOCTL) -- fprintf(stderr, "%s\n", __FUNCTION__); +-void radeonFlush( GLcontext *ctx ) +-{ +- radeonContextPtr rmesa = RADEON_CONTEXT( ctx ); + if ( mask & BUFFER_BIT_DEPTH ) { + flags |= RADEON_DEPTH; + mask &= ~BUFFER_BIT_DEPTH; + } -- if (rmesa->dma.flush) -- rmesa->dma.flush( rmesa ); -+ if ( (mask & BUFFER_BIT_STENCIL) && rmesa->radeon.state.stencil.hwBuffer ) { +- if (RADEON_DEBUG & DEBUG_IOCTL) +- fprintf(stderr, "%s\n", __FUNCTION__); ++ if ( (mask & BUFFER_BIT_STENCIL) ) { + flags |= RADEON_STENCIL; + mask &= ~BUFFER_BIT_STENCIL; + } +- if (rmesa->dma.flush) +- rmesa->dma.flush( rmesa ); ++ if ( mask ) { ++ if (RADEON_DEBUG & DEBUG_FALLBACKS) ++ fprintf(stderr, "%s: swrast clear, mask: %x\n", __FUNCTION__, mask); ++ _swrast_Clear( ctx, mask ); ++ } + - radeonEmitState( rmesa ); - - if (rmesa->store.cmd_used) - radeonFlushCmdBuf( rmesa, __FUNCTION__ ); -} -+ if ( mask ) { -+ if (RADEON_DEBUG & DEBUG_FALLBACKS) -+ fprintf(stderr, "%s: swrast clear, mask: %x\n", __FUNCTION__, mask); -+ _swrast_Clear( ctx, mask ); -+ } ++ if ( !flags ) ++ return; -/* Make sure all commands have been sent to the hardware and have - * completed processing. @@ -27089,15 +27834,11 @@ index 09acf6b..22584f4 100644 - radeonEmitIrqLocked( rmesa ); - UNLOCK_HARDWARE( rmesa ); - radeonWaitIrq( rmesa ); -+ if ( !flags ) -+ return; -+ + if (rmesa->using_hyperz) { + flags |= RADEON_USE_COMP_ZBUF; +/* if (rmesa->radeon.radeonScreen->chipset & RADEON_CHIPSET_TCL) + flags |= RADEON_USE_HIERZ; */ -+ if (!(rmesa->radeon.state.stencil.hwBuffer) || -+ ((flags & RADEON_DEPTH) && (flags & RADEON_STENCIL) && ++ if (((flags & RADEON_DEPTH) && (flags & RADEON_STENCIL) && + ((rmesa->radeon.state.stencil.clear & RADEON_STENCIL_WRITE_MASK) == RADEON_STENCIL_WRITE_MASK))) { + flags |= RADEON_CLEAR_FASTZ; + } @@ -28218,10 +28959,10 @@ index 126d072..d468a97 100644 } diff --git a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c new file mode 100644 -index 0000000..3203ee1 +index 0000000..228629e --- /dev/null +++ b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c -@@ -0,0 +1,360 @@ +@@ -0,0 +1,386 @@ +/* + * Copyright (C) 2008 Nicolai Haehnle. + * @@ -28582,12 +29323,38 @@ index 0000000..3203ee1 + texImage->Width, texImage->Height, texImage->Depth, + texImage->TexFormat->TexelBytes, t->tile_bits, compressed); +} ++ ++/* Although we use the image_offset[] array to store relative offsets ++ * to cube faces, Mesa doesn't know anything about this and expects ++ * each cube face to be treated as a separate image. ++ * ++ * These functions present that view to mesa: ++ */ ++const GLuint * ++radeon_miptree_depth_offsets(radeon_mipmap_tree *mt, GLuint level) ++{ ++ static const GLuint zero = 0; ++ if (mt->target != GL_TEXTURE_3D || mt->faces == 1) ++ return &zero; ++ else ++ return mt->levels[level].faces[0].offset; ++} ++ ++GLuint ++radeon_miptree_image_offset(radeon_mipmap_tree *mt, ++ GLuint face, GLuint level) ++{ ++ if (mt->target == GL_TEXTURE_CUBE_MAP_ARB) ++ return (mt->levels[level].faces[face].offset); ++ else ++ return mt->levels[level].faces[0].offset; ++} diff --git a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.h b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.h new file mode 100644 -index 0000000..43dfa48 +index 0000000..d9ad5ad --- /dev/null +++ b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.h -@@ -0,0 +1,97 @@ +@@ -0,0 +1,99 @@ +/* + * Copyright (C) 2008 Nicolai Haehnle. + * @@ -28682,8 +29449,10 @@ index 0000000..43dfa48 +GLboolean radeon_miptree_matches_texture(radeon_mipmap_tree *mt, struct gl_texture_object *texObj); +void radeon_try_alloc_miptree(radeonContextPtr rmesa, radeonTexObj *t, + struct gl_texture_image *texImage, GLuint face, GLuint level); -+ -+ ++GLuint radeon_miptree_image_offset(radeon_mipmap_tree *mt, ++ GLuint face, GLuint level); ++const GLuint * ++radeon_miptree_depth_offsets(radeon_mipmap_tree *mt, GLuint level); +#endif /* __RADEON_MIPMAP_TREE_H_ */ diff --git a/src/mesa/drivers/dri/radeon/radeon_sanity.c b/src/mesa/drivers/dri/radeon/radeon_sanity.c index 6613757..bbed838 100644 @@ -28712,7 +29481,7 @@ index 1ec06bc..f30eb1c 100644 drm_clip_rect_t *boxes ); diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c -index e964feb..bbcf19c 100644 +index e964feb..3817007 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -35,6 +35,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. @@ -28821,7 +29590,15 @@ index e964feb..bbcf19c 100644 static const struct dri_debug_control debug_control[] = { {"fall", DEBUG_FALLBACKS}, -@@ -330,6 +335,12 @@ static const __DRItexOffsetExtension radeonTexOffsetExtension = { +@@ -236,6 +241,7 @@ static const struct dri_debug_control debug_control[] = { + #endif /* RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) */ + + extern const struct dri_extension card_extensions[]; ++extern const struct dri_extension mm_extensions[]; + + static int getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo ); + +@@ -330,6 +336,12 @@ static const __DRItexOffsetExtension radeonTexOffsetExtension = { { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, radeonSetTexOffset, }; @@ -28834,7 +29611,7 @@ index e964feb..bbcf19c 100644 #endif #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) -@@ -344,6 +355,12 @@ static const __DRItexOffsetExtension r200texOffsetExtension = { +@@ -344,6 +356,12 @@ static const __DRItexOffsetExtension r200texOffsetExtension = { { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, r200SetTexOffset, }; @@ -28847,7 +29624,7 @@ index e964feb..bbcf19c 100644 #endif #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) -@@ -351,137 +368,18 @@ static const __DRItexOffsetExtension r300texOffsetExtension = { +@@ -351,137 +369,18 @@ static const __DRItexOffsetExtension r300texOffsetExtension = { { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, r300SetTexOffset, }; @@ -28993,7 +29770,7 @@ index e964feb..bbcf19c 100644 case PCI_CHIP_RADEON_LY: case PCI_CHIP_RADEON_LZ: case PCI_CHIP_RADEON_QY: -@@ -819,9 +717,162 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) +@@ -819,9 +718,162 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) default: fprintf(stderr, "unknown chip id 0x%x, can't guess.\n", @@ -29157,7 +29934,7 @@ index e964feb..bbcf19c 100644 if ((screen->chip_family == CHIP_FAMILY_R350 || screen->chip_family == CHIP_FAMILY_R300) && sPriv->ddx_version.minor < 2) { fprintf(stderr, "xf86-video-ati-6.6.2 or newer needed for Radeon 9500/9700/9800 cards.\n"); -@@ -849,7 +900,7 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) +@@ -849,7 +901,7 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) ret = radeonGetParam( sPriv->fd, RADEON_PARAM_FB_LOCATION, &temp); if (ret) { @@ -29166,12 +29943,13 @@ index e964feb..bbcf19c 100644 screen->fbLocation = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff) << 16; else { FREE( screen ); -@@ -951,26 +1002,127 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) +@@ -951,26 +1003,161 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) screen->extensions[i++] = &driMediaStreamCounterExtension.base; } + if (!screen->kernel_mm) { -+#if !RADEON_COMMON + #if !RADEON_COMMON +- screen->extensions[i++] = &radeonTexOffsetExtension.base; + screen->extensions[i++] = &radeonTexOffsetExtension.base; +#endif + @@ -29214,6 +29992,7 @@ index e964feb..bbcf19c 100644 + int i; + int ret; + uint32_t device_id; ++ uint32_t temp = 0; + + /* Allocate the private area */ + screen = (radeonScreenPtr) CALLOC( sizeof(*screen) ); @@ -29250,6 +30029,36 @@ index e964feb..bbcf19c 100644 + if (ret == -1) + return NULL; + ++ if (screen->chip_family >= CHIP_FAMILY_R300) { ++ ret = radeonGetParam( sPriv->fd, RADEON_PARAM_NUM_GB_PIPES, ++ &temp); ++ if (ret) { ++ fprintf(stderr, "Unable to get num_pipes, need newer drm\n"); ++ switch (screen->chip_family) { ++ case CHIP_FAMILY_R300: ++ case CHIP_FAMILY_R350: ++ screen->num_gb_pipes = 2; ++ break; ++ case CHIP_FAMILY_R420: ++ case CHIP_FAMILY_R520: ++ case CHIP_FAMILY_R580: ++ case CHIP_FAMILY_RV560: ++ case CHIP_FAMILY_RV570: ++ screen->num_gb_pipes = 4; ++ break; ++ case CHIP_FAMILY_RV350: ++ case CHIP_FAMILY_RV515: ++ case CHIP_FAMILY_RV530: ++ case CHIP_FAMILY_RV410: ++ default: ++ screen->num_gb_pipes = 1; ++ break; ++ } ++ } else { ++ screen->num_gb_pipes = temp; ++ } ++ } ++ + if (screen->chip_family <= CHIP_FAMILY_RS200) + screen->chip_flags |= RADEON_CLASS_R100; + else if (screen->chip_family <= CHIP_FAMILY_RV280) @@ -29257,6 +30066,9 @@ index e964feb..bbcf19c 100644 + else + screen->chip_flags |= RADEON_CLASS_R300; + ++ if (getenv("R300_NO_TCL")) ++ screen->chip_flags &= ~RADEON_CHIPSET_TCL; ++ + i = 0; + screen->extensions[i++] = &driCopySubBufferExtension.base; + screen->extensions[i++] = &driFrameTrackingExtension.base; @@ -29267,8 +30079,7 @@ index e964feb..bbcf19c 100644 + screen->extensions[i++] = &driMediaStreamCounterExtension.base; + } + - #if !RADEON_COMMON -- screen->extensions[i++] = &radeonTexOffsetExtension.base; ++#if !RADEON_COMMON + screen->extensions[i++] = &radeonTexBufferExtension.base; #endif @@ -29298,7 +30109,7 @@ index e964feb..bbcf19c 100644 return screen; } -@@ -979,23 +1131,32 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) +@@ -979,23 +1166,32 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) static void radeonDestroyScreen( __DRIscreenPrivate *sPriv ) { @@ -29344,7 +30155,7 @@ index e964feb..bbcf19c 100644 } -@@ -1004,15 +1165,103 @@ radeonDestroyScreen( __DRIscreenPrivate *sPriv ) +@@ -1004,16 +1200,21 @@ radeonDestroyScreen( __DRIscreenPrivate *sPriv ) static GLboolean radeonInitDriver( __DRIscreenPrivate *sPriv ) { @@ -29367,100 +30178,16 @@ index e964feb..bbcf19c 100644 + return GL_TRUE; } -+static GLboolean -+radeon_alloc_window_storage(GLcontext *ctx, struct gl_renderbuffer *rb, -+ GLenum intFormat, GLuint w, GLuint h) -+{ -+ rb->Width = w; -+ rb->Height = h; -+ rb->_ActualFormat = intFormat; -+ -+ return GL_TRUE; -+} -+ -+ -+static struct radeon_renderbuffer * -+radeon_create_renderbuffer(GLenum format, __DRIdrawablePrivate *driDrawPriv) -+{ -+ struct radeon_renderbuffer *ret; -+ -+ ret = CALLOC_STRUCT(radeon_renderbuffer); -+ if (!ret) -+ return NULL; -+ -+ _mesa_init_renderbuffer(&ret->base, 0); -+ ret->base.ClassID = RADEON_RB_CLASS; -+ -+ /* XXX format junk */ -+ switch (format) { -+ case GL_RGB5: -+ ret->base._ActualFormat = GL_RGB5; -+ ret->base._BaseFormat = GL_RGBA; -+ ret->base.RedBits = 5; -+ ret->base.GreenBits = 6; -+ ret->base.BlueBits = 5; -+ ret->base.DataType = GL_UNSIGNED_BYTE; -+ break; -+ case GL_RGBA8: -+ ret->base._ActualFormat = GL_RGBA8; -+ ret->base._BaseFormat = GL_RGBA; -+ ret->base.RedBits = 8; -+ ret->base.GreenBits = 8; -+ ret->base.BlueBits = 8; -+ ret->base.AlphaBits = 8; -+ ret->base.DataType = GL_UNSIGNED_BYTE; -+ break; -+ case GL_STENCIL_INDEX8_EXT: -+ ret->base._ActualFormat = GL_STENCIL_INDEX8_EXT; -+ ret->base._BaseFormat = GL_STENCIL_INDEX; -+ ret->base.StencilBits = 8; -+ ret->base.DataType = GL_UNSIGNED_BYTE; -+ break; -+ case GL_DEPTH_COMPONENT16: -+ ret->base._ActualFormat = GL_DEPTH_COMPONENT16; -+ ret->base._BaseFormat = GL_DEPTH_COMPONENT; -+ ret->base.DepthBits = 16; -+ ret->base.DataType = GL_UNSIGNED_SHORT; -+ break; -+ case GL_DEPTH_COMPONENT24: -+ ret->base._ActualFormat = GL_DEPTH24_STENCIL8_EXT; -+ ret->base._BaseFormat = GL_DEPTH_COMPONENT; -+ ret->base.DepthBits = 24; -+ ret->base.DataType = GL_UNSIGNED_INT; -+ break; -+ case GL_DEPTH24_STENCIL8_EXT: -+ ret->base._ActualFormat = GL_DEPTH24_STENCIL8_EXT; -+ ret->base._BaseFormat = GL_DEPTH_STENCIL_EXT; -+ ret->base.DepthBits = 24; -+ ret->base.StencilBits = 8; -+ ret->base.DataType = GL_UNSIGNED_INT_24_8_EXT; -+ break; -+ default: -+ fprintf(stderr, "%s: Unknown format 0x%04x\n", __FUNCTION__, format); -+ _mesa_delete_renderbuffer(&ret->base); -+ return NULL; -+ } -+ -+ ret->dPriv = driDrawPriv; -+ ret->base.InternalFormat = format; -+ -+ ret->base.AllocStorage = radeon_alloc_window_storage; -+ -+ radeonSetSpanFunctions(ret); -+ -+ ret->bo = NULL; -+ return ret; -+} ++ /** * Create the Mesa framebuffer and renderbuffers for a given window/drawable. -@@ -1026,98 +1275,94 @@ radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv, + * +@@ -1026,98 +1227,91 @@ radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv, const __GLcontextModes *mesaVis, GLboolean isPixmap ) { - radeonScreenPtr screen = (radeonScreenPtr) driScrnPriv->private; -- -- if (isPixmap) { + radeonScreenPtr screen = (radeonScreenPtr) driScrnPriv->private; + + const GLboolean swDepth = GL_FALSE; @@ -29469,9 +30196,9 @@ index e964feb..bbcf19c 100644 + const GLboolean swStencil = mesaVis->stencilBits > 0 && + mesaVis->depthBits != 24; + GLenum rgbFormat = (mesaVis->redBits == 5 ? GL_RGB5 : GL_RGBA8); -+ GLenum depthFormat = GL_NONE; + struct radeon_framebuffer *rfb; -+ + +- if (isPixmap) { + if (isPixmap) return GL_FALSE; /* not implemented */ - } @@ -29546,11 +30273,36 @@ index e964feb..bbcf19c 100644 - radeonSetSpanFunctions(stencilRb, mesaVis); - _mesa_add_renderbuffer(fb, BUFFER_STENCIL, &stencilRb->Base); - stencilRb->depthHasSurface = screen->depthHasSurface; -- } -+ if (mesaVis->depthBits == 16) -+ depthFormat = GL_DEPTH_COMPONENT16; -+ else if (mesaVis->depthBits == 24) -+ depthFormat = GL_DEPTH_COMPONENT24; ++ /* front color renderbuffer */ ++ rfb->color_rb[0] = radeon_create_renderbuffer(rgbFormat, driDrawPriv); ++ _mesa_add_renderbuffer(&rfb->base, BUFFER_FRONT_LEFT, &rfb->color_rb[0]->base); ++ rfb->color_rb[0]->has_surface = 1; ++ ++ /* back color renderbuffer */ ++ if (mesaVis->doubleBufferMode) { ++ rfb->color_rb[1] = radeon_create_renderbuffer(rgbFormat, driDrawPriv); ++ _mesa_add_renderbuffer(&rfb->base, BUFFER_BACK_LEFT, &rfb->color_rb[1]->base); ++ rfb->color_rb[1]->has_surface = 1; ++ } ++ ++ if (mesaVis->depthBits == 24) { ++ if (mesaVis->stencilBits == 8) { ++ struct radeon_renderbuffer *depthStencilRb = radeon_create_renderbuffer(GL_DEPTH24_STENCIL8_EXT, driDrawPriv); ++ _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depthStencilRb->base); ++ _mesa_add_renderbuffer(&rfb->base, BUFFER_STENCIL, &depthStencilRb->base); ++ depthStencilRb->has_surface = screen->depthHasSurface; ++ } else { ++ /* depth renderbuffer */ ++ struct radeon_renderbuffer *depth = radeon_create_renderbuffer(GL_DEPTH_COMPONENT24, driDrawPriv); ++ _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depth->base); ++ depth->has_surface = screen->depthHasSurface; + } ++ } else if (mesaVis->depthBits == 16) { ++ /* just 16-bit depth buffer, no hw stencil */ ++ struct radeon_renderbuffer *depth = radeon_create_renderbuffer(GL_DEPTH_COMPONENT16, driDrawPriv); ++ _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depth->base); ++ depth->has_surface = screen->depthHasSurface; ++ } - _mesa_add_soft_renderbuffers(fb, - GL_FALSE, /* color */ @@ -29560,37 +30312,6 @@ index e964feb..bbcf19c 100644 - swAlpha, - GL_FALSE /* aux */); - driDrawPriv->driverPrivate = (void *) fb; -+ /* front color renderbuffer */ -+ rfb->color_rb[0] = radeon_create_renderbuffer(rgbFormat, driDrawPriv); -+ _mesa_add_renderbuffer(&rfb->base, BUFFER_FRONT_LEFT, &rfb->color_rb[0]->base); -+ rfb->color_rb[0]->has_surface = 1; - -- return (driDrawPriv->driverPrivate != NULL); -- } --} -+ /* back color renderbuffer */ -+ if (mesaVis->doubleBufferMode) { -+ rfb->color_rb[1] = radeon_create_renderbuffer(rgbFormat, driDrawPriv); -+ _mesa_add_renderbuffer(&rfb->base, BUFFER_BACK_LEFT, &rfb->color_rb[1]->base); -+ rfb->color_rb[1]->has_surface = 1; -+ } - -+ /* depth renderbuffer */ -+ if (depthFormat != GL_NONE) { -+ struct radeon_renderbuffer *depth = -+ radeon_create_renderbuffer(depthFormat, driDrawPriv); -+ _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depth->base); -+ depth->has_surface = screen->depthHasSurface; -+ } -+ -+ /* stencil renderbuffer */ -+ if (mesaVis->stencilBits > 0 && !swStencil) { -+ struct radeon_renderbuffer *stencil = -+ radeon_create_renderbuffer(GL_STENCIL_INDEX8_EXT, driDrawPriv); -+ _mesa_add_renderbuffer(&rfb->base, BUFFER_STENCIL, &stencil->base); -+ stencil->has_surface = screen->depthHasSurface; -+ } -+ + _mesa_add_soft_renderbuffers(&rfb->base, + GL_FALSE, /* color */ + swDepth, @@ -29599,10 +30320,13 @@ index e964feb..bbcf19c 100644 + swAlpha, + GL_FALSE /* aux */); + driDrawPriv->driverPrivate = (void *) rfb; -+ -+ return (driDrawPriv->driverPrivate != NULL); -+} +- return (driDrawPriv->driverPrivate != NULL); +- } ++ return (driDrawPriv->driverPrivate != NULL); + } + +- static void radeonDestroyBuffer(__DRIdrawablePrivate *driDrawPriv) { @@ -29630,7 +30354,7 @@ index e964feb..bbcf19c 100644 } #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) -@@ -1211,13 +1456,102 @@ radeonInitScreen(__DRIscreenPrivate *psp) +@@ -1211,13 +1405,103 @@ radeonInitScreen(__DRIscreenPrivate *psp) if (!radeonInitDriver(psp)) return NULL; @@ -29676,6 +30400,7 @@ index e964feb..bbcf19c 100644 + * Hello chicken. Hello egg. How are you two today? + */ + driInitExtensions( NULL, card_extensions, GL_FALSE ); ++ driInitExtensions( NULL, mm_extensions, GL_FALSE ); +#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) + driInitExtensions( NULL, blend_extensions, GL_FALSE ); + driInitSingleExtension( NULL, ARB_vp_extension ); @@ -29735,7 +30460,7 @@ index e964feb..bbcf19c 100644 /** * Get information about previous buffer swaps. -@@ -1225,25 +1559,21 @@ radeonInitScreen(__DRIscreenPrivate *psp) +@@ -1225,25 +1509,21 @@ radeonInitScreen(__DRIscreenPrivate *psp) static int getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo ) { @@ -29771,7 +30496,7 @@ index e964feb..bbcf19c 100644 : 0.0; return 0; -@@ -1266,6 +1596,8 @@ const struct __DriverAPIRec driDriverAPI = { +@@ -1266,6 +1546,8 @@ const struct __DriverAPIRec driDriverAPI = { .WaitForSBC = NULL, .SwapBuffersMSC = NULL, .CopySubBuffer = radeonCopySubBuffer, @@ -29780,7 +30505,7 @@ index e964feb..bbcf19c 100644 }; #else const struct __DriverAPIRec driDriverAPI = { -@@ -1275,14 +1607,16 @@ const struct __DriverAPIRec driDriverAPI = { +@@ -1275,14 +1557,16 @@ const struct __DriverAPIRec driDriverAPI = { .DestroyContext = r200DestroyContext, .CreateBuffer = radeonCreateBuffer, .DestroyBuffer = radeonDestroyBuffer, @@ -29829,10 +30554,10 @@ index b84c70b..1c0f5bb 100644 #define IS_R100_CLASS(screen) \ diff --git a/src/mesa/drivers/dri/radeon/radeon_span.c b/src/mesa/drivers/dri/radeon/radeon_span.c -index 12051ff..49ec2c3 100644 +index 12051ff..3d2c5da 100644 --- a/src/mesa/drivers/dri/radeon/radeon_span.c +++ b/src/mesa/drivers/dri/radeon/radeon_span.c -@@ -43,37 +43,168 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +@@ -43,46 +43,190 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "main/glheader.h" #include "swrast/swrast.h" @@ -29848,19 +30573,17 @@ index 12051ff..49ec2c3 100644 #define DBG 0 ++static void radeonSetSpanFunctions(struct radeon_renderbuffer *rrb); ++ +static GLubyte *radeon_ptr32(const struct radeon_renderbuffer * rrb, + GLint x, GLint y) +{ + GLubyte *ptr = rrb->bo->ptr; -+ const __DRIdrawablePrivate *dPriv = rrb->dPriv; + uint32_t mask = RADEON_BO_FLAGS_MACRO_TILE | RADEON_BO_FLAGS_MICRO_TILE; + GLint offset; + GLint nmacroblkpl; + GLint nmicroblkpl; + -+ x += dPriv->x; -+ y += dPriv->y; -+ + if (rrb->has_surface || !(rrb->bo->flags & mask)) { + offset = x * rrb->cpp + y * rrb->pitch; + } else { @@ -29896,15 +30619,11 @@ index 12051ff..49ec2c3 100644 + GLint x, GLint y) +{ + GLubyte *ptr = rrb->bo->ptr; -+ const __DRIdrawablePrivate *dPriv = rrb->dPriv; + uint32_t mask = RADEON_BO_FLAGS_MACRO_TILE | RADEON_BO_FLAGS_MICRO_TILE; + GLint offset; + GLint nmacroblkpl; + GLint nmicroblkpl; + -+ x += dPriv->x; -+ y += dPriv->y; -+ + if (rrb->has_surface || !(rrb->bo->flags & mask)) { + offset = x * rrb->cpp + y * rrb->pitch; + } else { @@ -29940,7 +30659,6 @@ index 12051ff..49ec2c3 100644 + GLint x, GLint y) +{ + GLubyte *ptr = rrb->bo->ptr; -+ const __DRIdrawablePrivate *dPriv = rrb->dPriv; + uint32_t mask = RADEON_BO_FLAGS_MACRO_TILE | RADEON_BO_FLAGS_MICRO_TILE; + GLint offset; + GLint microblkxs; @@ -29948,9 +30666,6 @@ index 12051ff..49ec2c3 100644 + GLint nmacroblkpl; + GLint nmicroblkpl; + -+ x += dPriv->x; -+ y += dPriv->y; -+ + if (rrb->has_surface || !(rrb->bo->flags & mask)) { + offset = x * rrb->cpp + y * rrb->pitch; + } else { @@ -29996,15 +30711,21 @@ index 12051ff..49ec2c3 100644 #define LOCAL_VARS \ - driRenderbuffer *drb = (driRenderbuffer *) rb; \ - const __DRIdrawablePrivate *dPriv = drb->dPriv; \ -+ struct radeon_renderbuffer *rrb = (void *) rb; \ -+ const __DRIdrawablePrivate *dPriv = rrb->dPriv; \ - const GLuint bottom = dPriv->h - 1; \ +- const GLuint bottom = dPriv->h - 1; \ - GLubyte *buf = (GLubyte *) drb->flippedData \ - + (dPriv->y * drb->flippedPitch + dPriv->x) * drb->cpp; \ - GLuint p; \ - (void) p; ++ struct radeon_context *radeon = RADEON_CONTEXT(ctx); \ ++ struct radeon_renderbuffer *rrb = (void *) rb; \ ++ const GLint yScale = ctx->DrawBuffer->Name ? 1 : -1; \ ++ const GLint yBias = ctx->DrawBuffer->Name ? 0 : rrb->base.Height - 1;\ ++ unsigned int num_cliprects; \ ++ struct drm_clip_rect *cliprects; \ ++ int x_off, y_off; \ + GLuint p; \ -+ (void)p; ++ (void)p; \ ++ radeon_get_cliprects(radeon, &cliprects, &num_cliprects, &x_off, &y_off); #define LOCAL_DEPTH_VARS \ - driRenderbuffer *drb = (driRenderbuffer *) rb; \ @@ -30013,31 +30734,69 @@ index 12051ff..49ec2c3 100644 - GLuint xo = dPriv->x; \ - GLuint yo = dPriv->y; \ - GLubyte *buf = (GLubyte *) drb->Base.Data; ++ struct radeon_context *radeon = RADEON_CONTEXT(ctx); \ + struct radeon_renderbuffer *rrb = (void *) rb; \ -+ const __DRIdrawablePrivate *dPriv = rrb->dPriv; \ -+ const GLuint bottom = dPriv->h - 1; ++ const GLint yScale = ctx->DrawBuffer->Name ? 1 : -1; \ ++ const GLint yBias = ctx->DrawBuffer->Name ? 0 : rrb->base.Height - 1;\ ++ unsigned int num_cliprects; \ ++ struct drm_clip_rect *cliprects; \ ++ int x_off, y_off; \ ++ radeon_get_cliprects(radeon, &cliprects, &num_cliprects, &x_off, &y_off); #define LOCAL_STENCIL_VARS LOCAL_DEPTH_VARS -@@ -94,7 +225,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +-#define Y_FLIP(Y) (bottom - (Y)) ++#define Y_FLIP(_y) ((_y) * yScale + yBias) + + #define HW_LOCK() + + #define HW_UNLOCK() + ++/* XXX FBO: this is identical to the macro in spantmp2.h except we get ++ * the cliprect info from the context, not the driDrawable. ++ * Move this into spantmp2.h someday. ++ */ ++#define HW_CLIPLOOP() \ ++ do { \ ++ int _nc = num_cliprects; \ ++ while ( _nc-- ) { \ ++ int minx = cliprects[_nc].x1 - x_off; \ ++ int miny = cliprects[_nc].y1 - y_off; \ ++ int maxx = cliprects[_nc].x2 - x_off; \ ++ int maxy = cliprects[_nc].y2 - y_off; ++ + /* ================================================================ + * Color buffer + */ +@@ -94,7 +238,17 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define TAG(x) radeon##x##_RGB565 #define TAG2(x,y) radeon##x##_RGB565##y -#define GET_PTR(X,Y) (buf + ((Y) * drb->flippedPitch + (X)) * 2) -+#define GET_PTR(X,Y) radeon_ptr16(rrb, (X), (Y)) ++#define GET_PTR(X,Y) radeon_ptr16(rrb, (X) + x_off, (Y) + y_off) ++#include "spantmp2.h" ++ ++/* 32 bit, xRGB8888 color spanline and pixel functions ++ */ ++#define SPANTMP_PIXEL_FMT GL_BGRA ++#define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV ++ ++#define TAG(x) radeon##x##_xRGB8888 ++#define TAG2(x,y) radeon##x##_xRGB8888##y ++#define GET_PTR(X,Y) radeon_ptr32(rrb, (X) + x_off, (Y) + y_off) #include "spantmp2.h" /* 32 bit, ARGB8888 color spanline and pixel functions -@@ -104,7 +235,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +@@ -104,7 +258,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define TAG(x) radeon##x##_ARGB8888 #define TAG2(x,y) radeon##x##_ARGB8888##y -#define GET_PTR(X,Y) (buf + ((Y) * drb->flippedPitch + (X)) * 4) -+#define GET_PTR(X,Y) radeon_ptr32(rrb, (X), (Y)) ++#define GET_PTR(X,Y) radeon_ptr32(rrb, (X) + x_off, (Y) + y_off) #include "spantmp2.h" /* ================================================================ -@@ -121,65 +252,15 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +@@ -121,65 +275,15 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * too... */ @@ -30097,21 +30856,21 @@ index 12051ff..49ec2c3 100644 #define WRITE_DEPTH( _x, _y, d ) \ - *(GLushort *)(buf + radeon_mba_z16( drb, _x + xo, _y + yo )) = d; -+ *(GLushort *)radeon_ptr(rrb, _x, _y) = d ++ *(GLushort *)radeon_ptr(rrb, _x + x_off, _y + y_off) = d #define READ_DEPTH( d, _x, _y ) \ - d = *(GLushort *)(buf + radeon_mba_z16( drb, _x + xo, _y + yo )); -+ d = *(GLushort *)radeon_ptr(rrb, _x, _y) ++ d = *(GLushort *)radeon_ptr(rrb, _x + x_off, _y + y_off) #define TAG(x) radeon##x##_z16 #include "depthtmp.h" -@@ -194,35 +275,36 @@ radeon_mba_z16(const driRenderbuffer * drb, GLint x, GLint y) +@@ -194,35 +298,36 @@ radeon_mba_z16(const driRenderbuffer * drb, GLint x, GLint y) #ifdef COMPILE_R300 #define WRITE_DEPTH( _x, _y, d ) \ do { \ - GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo ); \ - GLuint tmp = *(GLuint *)(buf + offset); \ -+ GLuint *_ptr = (GLuint*)radeon_ptr32( rrb, _x, _y ); \ ++ GLuint *_ptr = (GLuint*)radeon_ptr32( rrb, _x + x_off, _y + y_off ); \ + GLuint tmp = *_ptr; \ tmp &= 0x000000ff; \ tmp |= ((d << 8) & 0xffffff00); \ @@ -30123,8 +30882,8 @@ index 12051ff..49ec2c3 100644 do { \ - GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo ); \ - GLuint tmp = *(GLuint *)(buf + offset); \ -+ GLuint *_ptr = (GLuint*)radeon_ptr32( rrb, _x, _y ); \ -+ GLuint tmp = *_ptr; \ ++ GLuint *_ptr = (GLuint*)radeon_ptr32( rrb, _x + x_off, _y + y_off ); \ ++ GLuint tmp = *_ptr; \ tmp &= 0xff000000; \ tmp |= ((d) & 0x00ffffff); \ - *(GLuint *)(buf + offset) = tmp; \ @@ -30137,13 +30896,13 @@ index 12051ff..49ec2c3 100644 do { \ - d = (*(GLuint *)(buf + radeon_mba_z32( drb, _x + xo, \ - _y + yo )) & 0xffffff00) >> 8; \ -+ d = (*(GLuint*)(radeon_ptr32(rrb, _x, _y)) & 0xffffff00) >> 8; \ ++ d = (*(GLuint*)(radeon_ptr32(rrb, _x + x_off, _y + y_off)) & 0xffffff00) >> 8; \ }while(0) #else #define READ_DEPTH( d, _x, _y ) \ - d = *(GLuint *)(buf + radeon_mba_z32( drb, _x + xo, \ - _y + yo )) & 0x00ffffff; -+ d = *(GLuint*)(radeon_ptr32(rrb, _x, _y )) & 0x00ffffff; ++ d = *(GLuint*)(radeon_ptr32(rrb, _x + x_off, _y + y_off )) & 0x00ffffff; #endif - +/* @@ -30153,13 +30912,13 @@ index 12051ff..49ec2c3 100644 #define TAG(x) radeon##x##_z24_s8 #include "depthtmp.h" -@@ -235,35 +317,35 @@ do { \ +@@ -235,35 +340,35 @@ do { \ #ifdef COMPILE_R300 #define WRITE_STENCIL( _x, _y, d ) \ do { \ - GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo ); \ - GLuint tmp = *(GLuint *)(buf + offset); \ -+ GLuint *_ptr = (GLuint*)radeon_ptr32(rrb, _x, _y); \ ++ GLuint *_ptr = (GLuint*)radeon_ptr32(rrb, _x + x_off, _y + y_off); \ + GLuint tmp = *_ptr; \ tmp &= 0xffffff00; \ tmp |= (d) & 0xff; \ @@ -30171,7 +30930,7 @@ index 12051ff..49ec2c3 100644 do { \ - GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo ); \ - GLuint tmp = *(GLuint *)(buf + offset); \ -+ GLuint *_ptr = (GLuint*)radeon_ptr32(rrb, _x, _y); \ ++ GLuint *_ptr = (GLuint*)radeon_ptr32(rrb, _x + x_off, _y + y_off); \ + GLuint tmp = *_ptr; \ tmp &= 0x00ffffff; \ tmp |= (((d) & 0xff) << 24); \ @@ -30185,7 +30944,7 @@ index 12051ff..49ec2c3 100644 do { \ - GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo ); \ - GLuint tmp = *(GLuint *)(buf + offset); \ -+ GLuint *_ptr = (GLuint*)radeon_ptr32( rrb, _x, _y ); \ ++ GLuint *_ptr = (GLuint*)radeon_ptr32( rrb, _x + x_off, _y + y_off ); \ + GLuint tmp = *_ptr; \ d = tmp & 0x000000ff; \ } while (0) @@ -30194,12 +30953,12 @@ index 12051ff..49ec2c3 100644 do { \ - GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo ); \ - GLuint tmp = *(GLuint *)(buf + offset); \ -+ GLuint *_ptr = (GLuint*)radeon_ptr32( rrb, _x, _y ); \ ++ GLuint *_ptr = (GLuint*)radeon_ptr32( rrb, _x + x_off, _y + y_off ); \ + GLuint tmp = *_ptr; \ d = (tmp & 0xff000000) >> 24; \ } while (0) #endif -@@ -271,20 +353,60 @@ do { \ +@@ -271,20 +376,84 @@ do { \ #define TAG(x) radeon##x##_z24_s8 #include "stenciltmp.h" @@ -30207,30 +30966,65 @@ index 12051ff..49ec2c3 100644 - * than doing this in HW_LOCK above). WaitForIdle() is the main - * culprit. - */ -+ -+static void map_buffer(struct gl_renderbuffer *rb, GLboolean write) + ++void map_unmap_rb(struct gl_renderbuffer *rb, int flag) +{ -+ struct radeon_renderbuffer *rrb = (void*)rb; ++ struct radeon_renderbuffer *rrb = radeon_renderbuffer(rb); + int r; + -+ if (rrb->bo) { -+ r = radeon_bo_map(rrb->bo, write); ++ if (rrb == NULL || !rrb->bo) ++ return; ++ ++ if (flag) { ++ r = radeon_bo_map(rrb->bo, 1); + if (r) { + fprintf(stderr, "(%s) error(%d) mapping buffer.\n", + __FUNCTION__, r); + } -+ } -+} + -+static void unmap_buffer(struct gl_renderbuffer *rb) -+{ -+ struct radeon_renderbuffer *rrb = (void*)rb; -+ -+ if (rrb->bo) { ++ radeonSetSpanFunctions(rrb); ++ } else { + radeon_bo_unmap(rrb->bo); ++ rb->GetRow = NULL; ++ rb->PutRow = NULL; + } +} - ++ ++static void ++radeon_map_unmap_buffers(GLcontext *ctx, GLboolean map) ++{ ++ radeonContextPtr rmesa = RADEON_CONTEXT(ctx); ++ GLuint i, j; ++ ++ /* color draw buffers */ ++ for (j = 0; j < ctx->DrawBuffer->_NumColorDrawBuffers; j++) ++ map_unmap_rb(ctx->DrawBuffer->_ColorDrawBuffers[j], map); ++ ++ /* check for render to textures */ ++ for (i = 0; i < BUFFER_COUNT; i++) { ++ struct gl_renderbuffer_attachment *att = ++ ctx->DrawBuffer->Attachment + i; ++ struct gl_texture_object *tex = att->Texture; ++ if (tex) { ++ /* render to texture */ ++ ASSERT(att->Renderbuffer); ++ if (map) ++ ctx->Driver.MapTexture(ctx, tex); ++ else ++ ctx->Driver.UnmapTexture(ctx, tex); ++ } ++ } ++ ++ map_unmap_rb(ctx->ReadBuffer->_ColorReadBuffer, map); ++ ++ /* depth buffer (Note wrapper!) */ ++ if (ctx->DrawBuffer->_DepthBuffer) ++ map_unmap_rb(ctx->DrawBuffer->_DepthBuffer->Wrapped, map); ++ ++ if (ctx->DrawBuffer->_StencilBuffer) ++ map_unmap_rb(ctx->DrawBuffer->_StencilBuffer->Wrapped, map); ++ ++} static void radeonSpanRenderStart(GLcontext * ctx) { radeonContextPtr rmesa = RADEON_CONTEXT(ctx); @@ -30249,18 +31043,7 @@ index 12051ff..49ec2c3 100644 + ctx->Driver.MapTexture(ctx, ctx->Texture.Unit[i]._Current); + } + -+ /* color draw buffers */ -+ for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) { -+ map_buffer(ctx->DrawBuffer->_ColorDrawBuffers[i], GL_TRUE); -+ } -+ -+ map_buffer(ctx->ReadBuffer->_ColorReadBuffer, GL_FALSE); -+ -+ if (ctx->DrawBuffer->_DepthBuffer) { -+ map_buffer(ctx->DrawBuffer->_DepthBuffer->Wrapped, GL_TRUE); -+ } -+ if (ctx->DrawBuffer->_StencilBuffer) -+ map_buffer(ctx->DrawBuffer->_StencilBuffer->Wrapped, GL_TRUE); ++ radeon_map_unmap_buffers(ctx, 1); + + /* The locking and wait for idle should really only be needed in classic mode. + * In a future memory manager based implementation, this should become @@ -30270,7 +31053,7 @@ index 12051ff..49ec2c3 100644 LOCK_HARDWARE(rmesa); radeonWaitForIdleLocked(rmesa); } -@@ -292,8 +414,25 @@ static void radeonSpanRenderStart(GLcontext * ctx) +@@ -292,8 +461,16 @@ static void radeonSpanRenderStart(GLcontext * ctx) static void radeonSpanRenderFinish(GLcontext * ctx) { radeonContextPtr rmesa = RADEON_CONTEXT(ctx); @@ -30283,25 +31066,16 @@ index 12051ff..49ec2c3 100644 + ctx->Driver.UnmapTexture(ctx, ctx->Texture.Unit[i]._Current); + } + -+ /* color draw buffers */ -+ for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) -+ unmap_buffer(ctx->DrawBuffer->_ColorDrawBuffers[i]); -+ -+ unmap_buffer(ctx->ReadBuffer->_ColorReadBuffer); -+ -+ if (ctx->DrawBuffer->_DepthBuffer) -+ unmap_buffer(ctx->DrawBuffer->_DepthBuffer->Wrapped); -+ if (ctx->DrawBuffer->_StencilBuffer) -+ unmap_buffer(ctx->DrawBuffer->_StencilBuffer->Wrapped); ++ radeon_map_unmap_buffers(ctx, 0); } void radeonInitSpanFuncs(GLcontext * ctx) -@@ -307,20 +446,17 @@ void radeonInitSpanFuncs(GLcontext * ctx) +@@ -307,20 +484,21 @@ void radeonInitSpanFuncs(GLcontext * ctx) /** * Plug in the Get/Put routines for the given driRenderbuffer. */ -void radeonSetSpanFunctions(driRenderbuffer * drb, const GLvisual * vis) -+void radeonSetSpanFunctions(struct radeon_renderbuffer *rrb) ++static void radeonSetSpanFunctions(struct radeon_renderbuffer *rrb) { - if (drb->Base.InternalFormat == GL_RGBA) { - if (vis->redBits == 5 && vis->greenBits == 6 @@ -30316,23 +31090,27 @@ index 12051ff..49ec2c3 100644 - radeonInitDepthPointers_z24_s8(&drb->Base); - } else if (drb->Base.InternalFormat == GL_STENCIL_INDEX8_EXT) { - radeonInitStencilPointers_z24_s8(&drb->Base); -+ if (rrb->base.InternalFormat == GL_RGB5) { ++ if (rrb->base._ActualFormat == GL_RGB5) { + radeonInitPointers_RGB565(&rrb->base); -+ } else if (rrb->base.InternalFormat == GL_RGBA8) { ++ } else if (rrb->base._ActualFormat == GL_RGB8) { ++ radeonInitPointers_xRGB8888(&rrb->base); ++ } else if (rrb->base._ActualFormat == GL_RGBA8) { + radeonInitPointers_ARGB8888(&rrb->base); -+ } else if (rrb->base.InternalFormat == GL_DEPTH_COMPONENT16) { ++ } else if (rrb->base._ActualFormat == GL_DEPTH_COMPONENT16) { + radeonInitDepthPointers_z16(&rrb->base); -+ } else if (rrb->base.InternalFormat == GL_DEPTH_COMPONENT24) { ++ } else if (rrb->base._ActualFormat == GL_DEPTH_COMPONENT24) { + radeonInitDepthPointers_z24_s8(&rrb->base); -+ } else if (rrb->base.InternalFormat == GL_STENCIL_INDEX8_EXT) { ++ } else if (rrb->base._ActualFormat == GL_DEPTH24_STENCIL8_EXT) { ++ radeonInitStencilPointers_z24_s8(&rrb->base); ++ } else if (rrb->base._ActualFormat == GL_STENCIL_INDEX8_EXT) { + radeonInitStencilPointers_z24_s8(&rrb->base); } } diff --git a/src/mesa/drivers/dri/radeon/radeon_span.h b/src/mesa/drivers/dri/radeon/radeon_span.h -index 9abe086..dd44ab5 100644 +index 9abe086..ea6a2e7 100644 --- a/src/mesa/drivers/dri/radeon/radeon_span.h +++ b/src/mesa/drivers/dri/radeon/radeon_span.h -@@ -42,9 +42,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +@@ -42,9 +42,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #ifndef __RADEON_SPAN_H__ #define __RADEON_SPAN_H__ @@ -30341,10 +31119,9 @@ index 9abe086..dd44ab5 100644 extern void radeonInitSpanFuncs(GLcontext * ctx); -extern void radeonSetSpanFunctions(driRenderbuffer * rb, const GLvisual * vis); -+extern void radeonSetSpanFunctions(struct radeon_renderbuffer *rrb); #endif diff --git a/src/mesa/drivers/dri/radeon/radeon_state.c b/src/mesa/drivers/dri/radeon/radeon_state.c -index 32bcff3..42b65cb 100644 +index 32bcff3..19ff268 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state.c +++ b/src/mesa/drivers/dri/radeon/radeon_state.c @@ -62,7 +62,7 @@ static void radeonUpdateSpecular( GLcontext *ctx ); @@ -30570,18 +31347,19 @@ index 32bcff3..42b65cb 100644 ctx->Color.ColorMask[RCOMP], ctx->Color.ColorMask[GCOMP], ctx->Color.ColorMask[BCOMP], -@@ -623,8 +527,8 @@ static void radeonColorMask( GLcontext *ctx, +@@ -623,8 +527,9 @@ static void radeonColorMask( GLcontext *ctx, static void radeonPolygonOffset( GLcontext *ctx, GLfloat factor, GLfloat units ) { - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); - float_ui32_type constant = { units * rmesa->state.depth.scale }; + r100ContextPtr rmesa = R100_CONTEXT(ctx); -+ float_ui32_type constant = { units * rmesa->radeon.state.depth.scale }; ++ const GLfloat depthScale = 1.0F / ctx->DrawBuffer->_DepthMaxF; ++ float_ui32_type constant = { units * depthScale }; float_ui32_type factoru = { factor }; RADEON_STATECHANGE( rmesa, zbs ); -@@ -634,7 +538,7 @@ static void radeonPolygonOffset( GLcontext *ctx, +@@ -634,7 +539,7 @@ static void radeonPolygonOffset( GLcontext *ctx, static void radeonPolygonStipple( GLcontext *ctx, const GLubyte *mask ) { @@ -30590,7 +31368,7 @@ index 32bcff3..42b65cb 100644 GLuint i; drm_radeon_stipple_t stipple; -@@ -646,27 +550,27 @@ static void radeonPolygonStipple( GLcontext *ctx, const GLubyte *mask ) +@@ -646,27 +551,27 @@ static void radeonPolygonStipple( GLcontext *ctx, const GLubyte *mask ) /* TODO: push this into cmd mechanism */ @@ -30624,7 +31402,7 @@ index 32bcff3..42b65cb 100644 radeonChooseRenderState( ctx ); radeonChooseVertexState( ctx ); } -@@ -686,7 +590,7 @@ static void radeonPolygonMode( GLcontext *ctx, GLenum face, GLenum mode ) +@@ -686,7 +591,7 @@ static void radeonPolygonMode( GLcontext *ctx, GLenum face, GLenum mode ) */ static void radeonUpdateSpecular( GLcontext *ctx ) { @@ -30633,7 +31411,7 @@ index 32bcff3..42b65cb 100644 uint32_t p = rmesa->hw.ctx.cmd[CTX_PP_CNTL]; GLuint flag = 0; -@@ -757,7 +661,7 @@ static void radeonUpdateSpecular( GLcontext *ctx ) +@@ -757,7 +662,7 @@ static void radeonUpdateSpecular( GLcontext *ctx ) /* Update vertex/render formats */ @@ -30642,7 +31420,7 @@ index 32bcff3..42b65cb 100644 radeonChooseRenderState( ctx ); radeonChooseVertexState( ctx ); } -@@ -774,7 +678,7 @@ static void radeonUpdateSpecular( GLcontext *ctx ) +@@ -774,7 +679,7 @@ static void radeonUpdateSpecular( GLcontext *ctx ) */ static void update_global_ambient( GLcontext *ctx ) { @@ -30651,7 +31429,7 @@ index 32bcff3..42b65cb 100644 float *fcmd = (float *)RADEON_DB_STATE( glt ); /* Need to do more if both emmissive & ambient are PREMULT: -@@ -809,7 +713,7 @@ static void update_light_colors( GLcontext *ctx, GLuint p ) +@@ -809,7 +714,7 @@ static void update_light_colors( GLcontext *ctx, GLuint p ) /* fprintf(stderr, "%s\n", __FUNCTION__); */ if (l->Enabled) { @@ -30660,7 +31438,7 @@ index 32bcff3..42b65cb 100644 float *fcmd = (float *)RADEON_DB_STATE( lit[p] ); COPY_4V( &fcmd[LIT_AMBIENT_RED], l->Ambient ); -@@ -849,7 +753,7 @@ static void check_twoside_fallback( GLcontext *ctx ) +@@ -849,7 +754,7 @@ static void check_twoside_fallback( GLcontext *ctx ) static void radeonColorMaterial( GLcontext *ctx, GLenum face, GLenum mode ) { @@ -30669,7 +31447,7 @@ index 32bcff3..42b65cb 100644 GLuint light_model_ctl1 = rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL]; light_model_ctl1 &= ~((3 << RADEON_EMISSIVE_SOURCE_SHIFT) | -@@ -913,7 +817,7 @@ static void radeonColorMaterial( GLcontext *ctx, GLenum face, GLenum mode ) +@@ -913,7 +818,7 @@ static void radeonColorMaterial( GLcontext *ctx, GLenum face, GLenum mode ) void radeonUpdateMaterial( GLcontext *ctx ) { @@ -30678,7 +31456,7 @@ index 32bcff3..42b65cb 100644 GLfloat (*mat)[4] = ctx->Light.Material.Attrib; GLfloat *fcmd = (GLfloat *)RADEON_DB_STATE( mtl ); GLuint mask = ~0; -@@ -978,7 +882,7 @@ void radeonUpdateMaterial( GLcontext *ctx ) +@@ -978,7 +883,7 @@ void radeonUpdateMaterial( GLcontext *ctx ) */ static void update_light( GLcontext *ctx ) { @@ -30687,7 +31465,7 @@ index 32bcff3..42b65cb 100644 /* Have to check these, or have an automatic shortcircuit mechanism * to remove noop statechanges. (Or just do a better job on the -@@ -1043,7 +947,7 @@ static void update_light( GLcontext *ctx ) +@@ -1043,7 +948,7 @@ static void update_light( GLcontext *ctx ) static void radeonLightfv( GLcontext *ctx, GLenum light, GLenum pname, const GLfloat *params ) { @@ -30696,7 +31474,7 @@ index 32bcff3..42b65cb 100644 GLint p = light - GL_LIGHT0; struct gl_light *l = &ctx->Light.Light[p]; GLfloat *fcmd = (GLfloat *)rmesa->hw.lit[p].cmd; -@@ -1164,7 +1068,7 @@ static void radeonLightfv( GLcontext *ctx, GLenum light, +@@ -1164,7 +1069,7 @@ static void radeonLightfv( GLcontext *ctx, GLenum light, static void radeonLightModelfv( GLcontext *ctx, GLenum pname, const GLfloat *param ) { @@ -30705,7 +31483,7 @@ index 32bcff3..42b65cb 100644 switch (pname) { case GL_LIGHT_MODEL_AMBIENT: -@@ -1188,7 +1092,7 @@ static void radeonLightModelfv( GLcontext *ctx, GLenum pname, +@@ -1188,7 +1093,7 @@ static void radeonLightModelfv( GLcontext *ctx, GLenum pname, check_twoside_fallback( ctx ); @@ -30714,7 +31492,7 @@ index 32bcff3..42b65cb 100644 radeonChooseRenderState( ctx ); radeonChooseVertexState( ctx ); } -@@ -1205,7 +1109,7 @@ static void radeonLightModelfv( GLcontext *ctx, GLenum pname, +@@ -1205,7 +1110,7 @@ static void radeonLightModelfv( GLcontext *ctx, GLenum pname, static void radeonShadeModel( GLcontext *ctx, GLenum mode ) { @@ -30723,7 +31501,7 @@ index 32bcff3..42b65cb 100644 GLuint s = rmesa->hw.set.cmd[SET_SE_CNTL]; s &= ~(RADEON_DIFFUSE_SHADE_MASK | -@@ -1244,7 +1148,7 @@ static void radeonShadeModel( GLcontext *ctx, GLenum mode ) +@@ -1244,7 +1149,7 @@ static void radeonShadeModel( GLcontext *ctx, GLenum mode ) static void radeonClipPlane( GLcontext *ctx, GLenum plane, const GLfloat *eq ) { GLint p = (GLint) plane - (GLint) GL_CLIP_PLANE0; @@ -30732,7 +31510,7 @@ index 32bcff3..42b65cb 100644 GLint *ip = (GLint *)ctx->Transform._ClipUserPlane[p]; RADEON_STATECHANGE( rmesa, ucp[p] ); -@@ -1256,7 +1160,7 @@ static void radeonClipPlane( GLcontext *ctx, GLenum plane, const GLfloat *eq ) +@@ -1256,7 +1161,7 @@ static void radeonClipPlane( GLcontext *ctx, GLenum plane, const GLfloat *eq ) static void radeonUpdateClipPlanes( GLcontext *ctx ) { @@ -30741,7 +31519,7 @@ index 32bcff3..42b65cb 100644 GLuint p; for (p = 0; p < ctx->Const.MaxClipPlanes; p++) { -@@ -1281,7 +1185,7 @@ static void +@@ -1281,7 +1186,7 @@ static void radeonStencilFuncSeparate( GLcontext *ctx, GLenum face, GLenum func, GLint ref, GLuint mask ) { @@ -30750,7 +31528,7 @@ index 32bcff3..42b65cb 100644 GLuint refmask = (((ctx->Stencil.Ref[0] & 0xff) << RADEON_STENCIL_REF_SHIFT) | ((ctx->Stencil.ValueMask[0] & 0xff) << RADEON_STENCIL_MASK_SHIFT)); -@@ -1325,7 +1229,7 @@ radeonStencilFuncSeparate( GLcontext *ctx, GLenum face, GLenum func, +@@ -1325,7 +1230,7 @@ radeonStencilFuncSeparate( GLcontext *ctx, GLenum face, GLenum func, static void radeonStencilMaskSeparate( GLcontext *ctx, GLenum face, GLuint mask ) { @@ -30759,7 +31537,7 @@ index 32bcff3..42b65cb 100644 RADEON_STATECHANGE( rmesa, msk ); rmesa->hw.msk.cmd[MSK_RB3D_STENCILREFMASK] &= ~RADEON_STENCIL_WRITE_MASK; -@@ -1336,7 +1240,7 @@ radeonStencilMaskSeparate( GLcontext *ctx, GLenum face, GLuint mask ) +@@ -1336,7 +1241,7 @@ radeonStencilMaskSeparate( GLcontext *ctx, GLenum face, GLuint mask ) static void radeonStencilOpSeparate( GLcontext *ctx, GLenum face, GLenum fail, GLenum zfail, GLenum zpass ) { @@ -30768,7 +31546,7 @@ index 32bcff3..42b65cb 100644 /* radeon 7200 have stencil bug, DEC and INC_WRAP will actually both do DEC_WRAP, and DEC_WRAP (and INVERT) will do INVERT. No way to get correct INC_WRAP and DEC, -@@ -1349,7 +1253,7 @@ static void radeonStencilOpSeparate( GLcontext *ctx, GLenum face, GLenum fail, +@@ -1349,7 +1254,7 @@ static void radeonStencilOpSeparate( GLcontext *ctx, GLenum face, GLenum fail, GLuint tempRADEON_STENCIL_ZPASS_DEC_WRAP; GLuint tempRADEON_STENCIL_ZPASS_INC_WRAP; @@ -30777,7 +31555,7 @@ index 32bcff3..42b65cb 100644 tempRADEON_STENCIL_FAIL_DEC_WRAP = RADEON_STENCIL_FAIL_DEC; tempRADEON_STENCIL_FAIL_INC_WRAP = RADEON_STENCIL_FAIL_INC; tempRADEON_STENCIL_ZFAIL_DEC_WRAP = RADEON_STENCIL_ZFAIL_DEC; -@@ -1455,9 +1359,9 @@ static void radeonStencilOpSeparate( GLcontext *ctx, GLenum face, GLenum fail, +@@ -1455,9 +1360,9 @@ static void radeonStencilOpSeparate( GLcontext *ctx, GLenum face, GLenum fail, static void radeonClearStencil( GLcontext *ctx, GLint s ) { @@ -30789,7 +31567,7 @@ index 32bcff3..42b65cb 100644 ((GLuint) (ctx->Stencil.Clear & 0xff) | (0xff << RADEON_STENCIL_MASK_SHIFT) | ((ctx->Stencil.WriteMask[0] & 0xff) << RADEON_STENCIL_WRITEMASK_SHIFT)); -@@ -1481,20 +1385,19 @@ static void radeonClearStencil( GLcontext *ctx, GLint s ) +@@ -1481,20 +1386,30 @@ static void radeonClearStencil( GLcontext *ctx, GLint s ) */ void radeonUpdateWindow( GLcontext *ctx ) { @@ -30802,21 +31580,34 @@ index 32bcff3..42b65cb 100644 + GLfloat xoffset = dPriv ? (GLfloat) dPriv->x : 0; + GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0; const GLfloat *v = ctx->Viewport._WindowMap.m; ++ const GLboolean render_to_fbo = (ctx->DrawBuffer ? (ctx->DrawBuffer->Name != 0) : 0); ++ const GLfloat depthScale = 1.0F / ctx->DrawBuffer->_DepthMaxF; ++ GLfloat y_scale, y_bias; ++ ++ if (render_to_fbo) { ++ y_scale = 1.0; ++ y_bias = 0; ++ } else { ++ y_scale = -1.0; ++ y_bias = yoffset; ++ } float_ui32_type sx = { v[MAT_SX] }; float_ui32_type tx = { v[MAT_TX] + xoffset + SUBPIXEL_X }; - float_ui32_type sy = { - v[MAT_SY] }; - float_ui32_type ty = { (- v[MAT_TY]) + yoffset + SUBPIXEL_Y }; +- float_ui32_type sy = { - v[MAT_SY] }; +- float_ui32_type ty = { (- v[MAT_TY]) + yoffset + SUBPIXEL_Y }; - float_ui32_type sz = { v[MAT_SZ] * rmesa->state.depth.scale }; - float_ui32_type tz = { v[MAT_TZ] * rmesa->state.depth.scale }; -+ float_ui32_type sz = { v[MAT_SZ] * rmesa->radeon.state.depth.scale }; -+ float_ui32_type tz = { v[MAT_TZ] * rmesa->radeon.state.depth.scale }; ++ float_ui32_type sy = { v[MAT_SY] * y_scale }; ++ float_ui32_type ty = { (v[MAT_TY] * y_scale) + y_bias + SUBPIXEL_Y }; ++ float_ui32_type sz = { v[MAT_SZ] * depthScale }; ++ float_ui32_type tz = { v[MAT_TZ] * depthScale }; - RADEON_FIREVERTICES( rmesa ); RADEON_STATECHANGE( rmesa, vpt ); rmesa->hw.vpt.cmd[VPT_SE_VPORT_XSCALE] = sx.ui32; -@@ -1514,6 +1417,8 @@ static void radeonViewport( GLcontext *ctx, GLint x, GLint y, +@@ -1514,6 +1429,8 @@ static void radeonViewport( GLcontext *ctx, GLint x, GLint y, * values, or keep the originals hanging around. */ radeonUpdateWindow( ctx ); @@ -30825,7 +31616,7 @@ index 32bcff3..42b65cb 100644 } static void radeonDepthRange( GLcontext *ctx, GLclampd nearval, -@@ -1524,8 +1429,8 @@ static void radeonDepthRange( GLcontext *ctx, GLclampd nearval, +@@ -1524,8 +1441,8 @@ static void radeonDepthRange( GLcontext *ctx, GLclampd nearval, void radeonUpdateViewportOffset( GLcontext *ctx ) { @@ -30836,7 +31627,7 @@ index 32bcff3..42b65cb 100644 GLfloat xoffset = (GLfloat)dPriv->x; GLfloat yoffset = (GLfloat)dPriv->y + dPriv->h; const GLfloat *v = ctx->Viewport._WindowMap.m; -@@ -1555,8 +1460,8 @@ void radeonUpdateViewportOffset( GLcontext *ctx ) +@@ -1555,8 +1472,8 @@ void radeonUpdateViewportOffset( GLcontext *ctx ) RADEON_STIPPLE_Y_OFFSET_MASK); /* add magic offsets, then invert */ @@ -30847,7 +31638,7 @@ index 32bcff3..42b65cb 100644 & RADEON_STIPPLE_COORD_MASK); m |= ((stx << RADEON_STIPPLE_X_OFFSET_SHIFT) | -@@ -1580,20 +1485,20 @@ void radeonUpdateViewportOffset( GLcontext *ctx ) +@@ -1580,20 +1497,20 @@ void radeonUpdateViewportOffset( GLcontext *ctx ) static void radeonClearColor( GLcontext *ctx, const GLfloat color[4] ) { @@ -30871,7 +31662,7 @@ index 32bcff3..42b65cb 100644 FALLBACK( rmesa, RADEON_FALLBACK_RENDER_MODE, (mode != GL_RENDER) ); } -@@ -1619,7 +1524,7 @@ static GLuint radeon_rop_tab[] = { +@@ -1619,7 +1536,7 @@ static GLuint radeon_rop_tab[] = { static void radeonLogicOpCode( GLcontext *ctx, GLenum opcode ) { @@ -30880,7 +31671,7 @@ index 32bcff3..42b65cb 100644 GLuint rop = (GLuint)opcode - GL_CLEAR; ASSERT( rop < 16 ); -@@ -1628,105 +1533,13 @@ static void radeonLogicOpCode( GLcontext *ctx, GLenum opcode ) +@@ -1628,105 +1545,13 @@ static void radeonLogicOpCode( GLcontext *ctx, GLenum opcode ) rmesa->hw.msk.cmd[MSK_RB3D_ROPCNTL] = radeon_rop_tab[rop]; } @@ -30987,7 +31778,7 @@ index 32bcff3..42b65cb 100644 GLuint p, flag; if ( RADEON_DEBUG & DEBUG_STATE ) -@@ -1821,10 +1634,10 @@ static void radeonEnable( GLcontext *ctx, GLenum cap, GLboolean state ) +@@ -1821,10 +1646,10 @@ static void radeonEnable( GLcontext *ctx, GLenum cap, GLboolean state ) RADEON_STATECHANGE(rmesa, ctx ); if ( state ) { rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_ENABLE; @@ -31000,7 +31791,7 @@ index 32bcff3..42b65cb 100644 } break; -@@ -1971,13 +1784,13 @@ static void radeonEnable( GLcontext *ctx, GLenum cap, GLboolean state ) +@@ -1971,21 +1796,30 @@ static void radeonEnable( GLcontext *ctx, GLenum cap, GLboolean state ) } case GL_SCISSOR_TEST: @@ -31013,11 +31804,34 @@ index 32bcff3..42b65cb 100644 case GL_STENCIL_TEST: - if ( rmesa->state.stencil.hwBuffer ) { -+ if ( rmesa->radeon.state.stencil.hwBuffer ) { - RADEON_STATECHANGE( rmesa, ctx ); - if ( state ) { - rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_STENCIL_ENABLE; -@@ -2010,7 +1823,7 @@ static void radeonEnable( GLcontext *ctx, GLenum cap, GLboolean state ) +- RADEON_STATECHANGE( rmesa, ctx ); +- if ( state ) { +- rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_STENCIL_ENABLE; ++ { ++ GLboolean hw_stencil = GL_FALSE; ++ if (ctx->DrawBuffer) { ++ struct radeon_renderbuffer *rrbStencil ++ = radeon_get_renderbuffer(ctx->DrawBuffer, BUFFER_STENCIL); ++ hw_stencil = (rrbStencil && rrbStencil->bo); ++ } ++ ++ if (hw_stencil) { ++ RADEON_STATECHANGE( rmesa, ctx ); ++ if ( state ) { ++ rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_STENCIL_ENABLE; ++ } else { ++ rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~RADEON_STENCIL_ENABLE; ++ } + } else { +- rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~RADEON_STENCIL_ENABLE; ++ FALLBACK( rmesa, RADEON_FALLBACK_STENCIL, state ); + } +- } else { +- FALLBACK( rmesa, RADEON_FALLBACK_STENCIL, state ); + } + break; + +@@ -2010,7 +1844,7 @@ static void radeonEnable( GLcontext *ctx, GLenum cap, GLboolean state ) static void radeonLightingSpaceChange( GLcontext *ctx ) { @@ -31026,7 +31840,7 @@ index 32bcff3..42b65cb 100644 GLboolean tmp; RADEON_STATECHANGE( rmesa, tcl ); -@@ -2039,7 +1852,7 @@ static void radeonLightingSpaceChange( GLcontext *ctx ) +@@ -2039,7 +1873,7 @@ static void radeonLightingSpaceChange( GLcontext *ctx ) */ @@ -31035,7 +31849,7 @@ index 32bcff3..42b65cb 100644 int unit, GLboolean swapcols ) { /* Here's how this works: on r100, only 3 tex coords can be submitted, so the -@@ -2065,7 +1878,7 @@ void radeonUploadTexMatrix( radeonContextPtr rmesa, +@@ -2065,7 +1899,7 @@ void radeonUploadTexMatrix( radeonContextPtr rmesa, int idx = TEXMAT_0 + unit; float *dest = ((float *)RADEON_DB_STATE( mat[idx] )) + MAT_ELT_0; int i; @@ -31044,7 +31858,7 @@ index 32bcff3..42b65cb 100644 GLfloat *src = rmesa->tmpmat[unit].m; rmesa->TexMatColSwap &= ~(1 << unit); -@@ -2119,7 +1932,7 @@ void radeonUploadTexMatrix( radeonContextPtr rmesa, +@@ -2119,7 +1953,7 @@ void radeonUploadTexMatrix( radeonContextPtr rmesa, } @@ -31053,7 +31867,7 @@ index 32bcff3..42b65cb 100644 { float *dest = ((float *)RADEON_DB_STATE( mat[idx] ))+MAT_ELT_0; int i; -@@ -2135,7 +1948,7 @@ static void upload_matrix( radeonContextPtr rmesa, GLfloat *src, int idx ) +@@ -2135,7 +1969,7 @@ static void upload_matrix( radeonContextPtr rmesa, GLfloat *src, int idx ) RADEON_DB_STATECHANGE( rmesa, &rmesa->hw.mat[idx] ); } @@ -31062,7 +31876,7 @@ index 32bcff3..42b65cb 100644 { float *dest = ((float *)RADEON_DB_STATE( mat[idx] ))+MAT_ELT_0; memcpy(dest, src, 16*sizeof(float)); -@@ -2145,7 +1958,7 @@ static void upload_matrix_t( radeonContextPtr rmesa, GLfloat *src, int idx ) +@@ -2145,7 +1979,7 @@ static void upload_matrix_t( radeonContextPtr rmesa, GLfloat *src, int idx ) static void update_texturematrix( GLcontext *ctx ) { @@ -31071,7 +31885,7 @@ index 32bcff3..42b65cb 100644 GLuint tpc = rmesa->hw.tcl.cmd[TCL_TEXTURE_PROC_CTL]; GLuint vs = rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXSEL]; int unit; -@@ -2210,58 +2023,21 @@ static void update_texturematrix( GLcontext *ctx ) +@@ -2210,58 +2044,21 @@ static void update_texturematrix( GLcontext *ctx ) } @@ -31137,7 +31951,7 @@ index 32bcff3..42b65cb 100644 } /* Need an event driven matrix update? -@@ -2295,7 +2071,7 @@ void radeonValidateState( GLcontext *ctx ) +@@ -2295,7 +2092,7 @@ void radeonValidateState( GLcontext *ctx ) } @@ -31146,7 +31960,7 @@ index 32bcff3..42b65cb 100644 } -@@ -2306,7 +2082,7 @@ static void radeonInvalidateState( GLcontext *ctx, GLuint new_state ) +@@ -2306,7 +2103,7 @@ static void radeonInvalidateState( GLcontext *ctx, GLuint new_state ) _vbo_InvalidateState( ctx, new_state ); _tnl_InvalidateState( ctx, new_state ); _ae_invalidate_state( ctx, new_state ); @@ -31155,7 +31969,7 @@ index 32bcff3..42b65cb 100644 } -@@ -2330,15 +2106,15 @@ static GLboolean check_material( GLcontext *ctx ) +@@ -2330,15 +2127,15 @@ static GLboolean check_material( GLcontext *ctx ) static void radeonWrapRunPipeline( GLcontext *ctx ) { @@ -31214,7 +32028,7 @@ index 2171879..17c2b11 100644 diff --git a/src/mesa/drivers/dri/radeon/radeon_state_init.c b/src/mesa/drivers/dri/radeon/radeon_state_init.c -index 57dc380..8b6caf1 100644 +index 57dc380..3d0cd8d 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state_init.c +++ b/src/mesa/drivers/dri/radeon/radeon_state_init.c @@ -38,39 +38,156 @@ @@ -31406,7 +32220,7 @@ index 57dc380..8b6caf1 100644 } -@@ -146,81 +263,379 @@ CHECK( txr0, (ctx->Texture.Unit[0]._ReallyEnabled & TEXTURE_RECT_BIT)) +@@ -146,81 +263,373 @@ CHECK( txr0, (ctx->Texture.Unit[0]._ReallyEnabled & TEXTURE_RECT_BIT)) CHECK( txr1, (ctx->Texture.Unit[1]._ReallyEnabled & TEXTURE_RECT_BIT)) CHECK( txr2, (ctx->Texture.Unit[2]._ReallyEnabled & TEXTURE_RECT_BIT)) @@ -31760,7 +32574,6 @@ index 57dc380..8b6caf1 100644 - depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z; - rmesa->state.stencil.clear = 0x00000000; + rmesa->radeon.state.depth.clear = 0x0000ffff; -+ rmesa->radeon.state.depth.scale = 1.0 / (GLfloat)0xffff; + rmesa->radeon.state.stencil.clear = 0x00000000; break; case 24: @@ -31769,7 +32582,6 @@ index 57dc380..8b6caf1 100644 - depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z; - rmesa->state.stencil.clear = 0xffff0000; + rmesa->radeon.state.depth.clear = 0x00ffffff; -+ rmesa->radeon.state.depth.scale = 1.0 / (GLfloat)0xffffff; + rmesa->radeon.state.stencil.clear = 0xffff0000; break; default: @@ -31779,11 +32591,10 @@ index 57dc380..8b6caf1 100644 + break; } - /* Only have hw stencil when depth buffer is 24 bits deep */ +- /* Only have hw stencil when depth buffer is 24 bits deep */ - rmesa->state.stencil.hwBuffer = ( ctx->Visual.stencilBits > 0 && -+ rmesa->radeon.state.stencil.hwBuffer = ( ctx->Visual.stencilBits > 0 && - ctx->Visual.depthBits == 24 ); - +- ctx->Visual.depthBits == 24 ); +- - rmesa->Fallback = 0; + rmesa->radeon.Fallback = 0; @@ -31832,7 +32643,7 @@ index 57dc380..8b6caf1 100644 ALLOC_STATE( lin, always, LIN_STATE_SIZE, "LIN/line", 0 ); ALLOC_STATE( msk, always, MSK_STATE_SIZE, "MSK/mask", 0 ); ALLOC_STATE( vpt, always, VPT_STATE_SIZE, "VPT/viewport", 0 ); -@@ -233,20 +648,29 @@ void radeonInitState( radeonContextPtr rmesa ) +@@ -233,20 +642,29 @@ void radeonInitState( radeonContextPtr rmesa ) ALLOC_STATE( fog, fog, FOG_STATE_SIZE, "FOG/fog", 1 ); ALLOC_STATE( glt, tcl_lighting, GLT_STATE_SIZE, "GLT/light-global", 1 ); ALLOC_STATE( eye, tcl_lighting, EYE_STATE_SIZE, "EYE/eye-vector", 1 ); @@ -31872,7 +32683,7 @@ index 57dc380..8b6caf1 100644 } ALLOC_STATE( mat[0], tcl, MAT_STATE_SIZE, "MAT/modelproject", 1 ); ALLOC_STATE( mat[1], tcl_eyespace_or_fog, MAT_STATE_SIZE, "MAT/modelview", 1 ); -@@ -268,43 +692,43 @@ void radeonInitState( radeonContextPtr rmesa ) +@@ -268,43 +686,43 @@ void radeonInitState( radeonContextPtr rmesa ) ALLOC_STATE( lit[5], tcl_lit5, LIT_STATE_SIZE, "LIT/light-5", 1 ); ALLOC_STATE( lit[6], tcl_lit6, LIT_STATE_SIZE, "LIT/light-6", 1 ); ALLOC_STATE( lit[7], tcl_lit7, LIT_STATE_SIZE, "LIT/light-7", 1 ); @@ -31947,7 +32758,7 @@ index 57dc380..8b6caf1 100644 rmesa->hw.grd.cmd[GRD_CMD_0] = cmdscl( RADEON_SS_VERT_GUARD_CLIP_ADJ_ADDR, 1, 4 ); rmesa->hw.fog.cmd[FOG_CMD_0] = -@@ -331,6 +755,22 @@ void radeonInitState( radeonContextPtr rmesa ) +@@ -331,6 +749,22 @@ void radeonInitState( radeonContextPtr rmesa ) cmdvec( RADEON_VS_UCP_ADDR + i, 1, 4 ); } @@ -31970,7 +32781,7 @@ index 57dc380..8b6caf1 100644 rmesa->last_ReallyEnabled = -1; /* Initial Harware state: -@@ -352,19 +792,7 @@ void radeonInitState( radeonContextPtr rmesa ) +@@ -352,19 +786,7 @@ void radeonInitState( radeonContextPtr rmesa ) RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ZERO ); @@ -31991,7 +32802,7 @@ index 57dc380..8b6caf1 100644 RADEON_STENCIL_TEST_ALWAYS | RADEON_STENCIL_FAIL_KEEP | RADEON_STENCIL_ZPASS_KEEP | -@@ -374,7 +802,7 @@ void radeonInitState( radeonContextPtr rmesa ) +@@ -374,7 +796,7 @@ void radeonInitState( radeonContextPtr rmesa ) if (rmesa->using_hyperz) { rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_COMPRESSION_ENABLE | RADEON_Z_DECOMPRESSION_ENABLE; @@ -32000,7 +32811,7 @@ index 57dc380..8b6caf1 100644 /* works for q3, but slight rendering errors with glxgears ? */ /* rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_HIERARCHY_ENABLE;*/ /* need this otherwise get lots of lockups with q3 ??? */ -@@ -386,10 +814,9 @@ void radeonInitState( radeonContextPtr rmesa ) +@@ -386,10 +808,9 @@ void radeonInitState( radeonContextPtr rmesa ) RADEON_ANTI_ALIAS_NONE); rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = (RADEON_PLANE_MASK_ENABLE | @@ -32012,7 +32823,7 @@ index 57dc380..8b6caf1 100644 case DRI_CONF_DITHER_XERRORDIFFRESET: rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_INIT; break; -@@ -397,30 +824,17 @@ void radeonInitState( radeonContextPtr rmesa ) +@@ -397,30 +818,17 @@ void radeonInitState( radeonContextPtr rmesa ) rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_SCALE_DITHER_ENABLE; break; } @@ -32048,7 +32859,7 @@ index 57dc380..8b6caf1 100644 rmesa->hw.set.cmd[SET_SE_CNTL] = (RADEON_FFACE_CULL_CCW | RADEON_BFACE_SOLID | -@@ -444,7 +858,7 @@ void radeonInitState( radeonContextPtr rmesa ) +@@ -444,7 +852,7 @@ void radeonInitState( radeonContextPtr rmesa ) RADEON_VC_NO_SWAP; #endif @@ -32057,7 +32868,7 @@ index 57dc380..8b6caf1 100644 rmesa->hw.set.cmd[SET_SE_CNTL_STATUS] |= RADEON_TCL_BYPASS; } -@@ -491,8 +905,8 @@ void radeonInitState( radeonContextPtr rmesa ) +@@ -491,8 +899,8 @@ void radeonInitState( radeonContextPtr rmesa ) (2 << RADEON_TXFORMAT_HEIGHT_SHIFT)); /* Initialize the texture offset to the start of the card texture heap */ @@ -32068,7 +32879,7 @@ index 57dc380..8b6caf1 100644 rmesa->hw.tex[i].cmd[TEX_PP_BORDER_COLOR] = 0; rmesa->hw.tex[i].cmd[TEX_PP_TXCBLEND] = -@@ -513,15 +927,15 @@ void radeonInitState( radeonContextPtr rmesa ) +@@ -513,15 +921,15 @@ void radeonInitState( radeonContextPtr rmesa ) rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_FACES] = 0; rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_0] = @@ -32089,7 +32900,7 @@ index 57dc380..8b6caf1 100644 } /* Can only add ST1 at the time of doing some multitex but can keep -@@ -613,5 +1027,7 @@ void radeonInitState( radeonContextPtr rmesa ) +@@ -613,5 +1021,7 @@ void radeonInitState( radeonContextPtr rmesa ) rmesa->hw.eye.cmd[EYE_Z] = IEEE_ONE; rmesa->hw.eye.cmd[EYE_RESCALE_FACTOR] = IEEE_ONE; @@ -33397,7 +34208,7 @@ index b0aec21..2dfb504 100644 driInitTextureFormats(); } diff --git a/src/mesa/drivers/dri/radeon/radeon_tex.h b/src/mesa/drivers/dri/radeon/radeon_tex.h -index 8000880..8d8afb4 100644 +index 8000880..a4aaddc 100644 --- a/src/mesa/drivers/dri/radeon/radeon_tex.h +++ b/src/mesa/drivers/dri/radeon/radeon_tex.h @@ -41,12 +41,16 @@ extern void radeonSetTexOffset(__DRIcontext *pDRICtx, GLint texname, @@ -34811,10 +35622,10 @@ index b165205..78e2a08 100644 } diff --git a/src/mesa/drivers/dri/radeon/radeon_texture.c b/src/mesa/drivers/dri/radeon/radeon_texture.c new file mode 100644 -index 0000000..63680b4 +index 0000000..d212898 --- /dev/null +++ b/src/mesa/drivers/dri/radeon/radeon_texture.c -@@ -0,0 +1,966 @@ +@@ -0,0 +1,969 @@ +/* + * Copyright (C) 2008 Nicolai Haehnle. + * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. @@ -34956,9 +35767,12 @@ index 0000000..63680b4 + radeonTexObj* t = radeon_tex_obj(texObj); + int face, level; + ++ if (!radeon_validate_texture_miptree(ctx, texObj)) ++ return; ++ + /* for r100 3D sw fallbacks don't have mt */ + if (!t->mt) -+ return; ++ return; + + radeon_bo_map(t->mt->bo, GL_FALSE); + for(face = 0; face < t->mt->faces; ++face) {