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Update patch "intel/compiler: reemit boolean resolve for inverted if on gen5"

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The patch has been accepted upstream with some minor changes.

Update it to match the version upstream.
This commit is contained in:
José Expósito 2024-01-08 10:59:58 +01:00
parent c5c4360da7
commit 07ce0166ac
1 changed files with 15 additions and 10 deletions
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25
0001-intel-compiler-reemit-boolean-resolve-for-inverted-i.patch
View file

@ -1,4 +1,4 @@
From c59f3601b81bf38cbb7a2b77820f1d827f608339 Mon Sep 17 00:00:00 2001
From 56a72e014fcda3c52cf119115cb71fce2fad86d8 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Thu, 21 Dec 2023 10:39:08 +1000
Subject: [PATCH] intel/compiler: reemit boolean resolve for inverted if on
@ -8,30 +8,35 @@ Gen5 adds some boolean conversion instructions after nir emits,
but that nir srcs don't line up with them, so reemit the boolean
conversion if we reemit the inot.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 31b5f5a51f3a ("nir/opt_if: Simplify if's with general conditions")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26782>
---
src/intel/compiler/brw_fs_nir.cpp | 8 ++++++++
1 file changed, 8 insertions(+)
src/intel/compiler/brw_fs_nir.cpp | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp
index b9f7366763b..5a4ec96e93f 100644
index 33f2a4046b2..ccdd0fe7db8 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -361,6 +361,14 @@ fs_visitor::nir_emit_if(nir_if *if_stmt)
@@ -422,6 +422,17 @@ fs_nir_emit_if(nir_to_brw_state &ntb, nir_if *if_stmt)
invert = true;
cond_reg = get_nir_src(cond->src[0].src);
cond_reg = get_nir_src(ntb, cond->src[0].src);
cond_reg = offset(cond_reg, bld, cond->src[0].swizzle[0]);
+
+ if (devinfo->ver <= 5) {
+ if (devinfo->ver <= 5 &&
+ (cond->instr.pass_flags & BRW_NIR_BOOLEAN_MASK) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE) {
+ /* redo boolean resolve on gen5 */
+ fs_reg masked = bld.vgrf(BRW_REGISTER_TYPE_D);
+ fs_reg masked = ntb.s.vgrf(glsl_int_type());
+ bld.AND(masked, cond_reg, brw_imm_d(1));
+ masked.negate = true;
+ bld.MOV(retype(cond_reg, BRW_REGISTER_TYPE_D), masked);
+ fs_reg tmp = bld.vgrf(cond_reg.type);
+ bld.MOV(retype(tmp, BRW_REGISTER_TYPE_D), masked);
+ cond_reg = tmp;
+ }
} else {
invert = false;
cond_reg = get_nir_src(if_stmt->condition);
cond_reg = get_nir_src(ntb, if_stmt->condition);
--
2.43.0