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126 lines
4.3 KiB
Diff
126 lines
4.3 KiB
Diff
From ffecacb1a1eeca8ca8567057c3c886161837d2a6 Mon Sep 17 00:00:00 2001
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From: Tom Stellard <thomas.stellard@amd.com>
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Date: Thu, 15 May 2014 20:55:58 +0000
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Subject: [PATCH 3/5] Merging r208501:
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------------------------------------------------------------------------
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r208501 | hfinkel | 2014-05-11 12:23:29 -0400 (Sun, 11 May 2014) | 9 lines
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[PowerPC] On PPC32, 128-bit shifts might be runtime calls
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The counter-loops formation pass needs to know what operations might be
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function calls (because they can't appear in counter-based loops). On PPC32,
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128-bit shifts might be runtime calls (even though you can't use __int128 on
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PPC32, it seems that SROA might form them).
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Fixes PR19709.
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------------------------------------------------------------------------
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@208916 91177308-0d34-0410-b5e6-96231b3b80d8
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---
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lib/Target/PowerPC/PPCCTRLoops.cpp | 8 +++++
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test/CodeGen/PowerPC/ctrloop-sh.ll | 72 ++++++++++++++++++++++++++++++++++++++
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2 files changed, 80 insertions(+)
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create mode 100644 test/CodeGen/PowerPC/ctrloop-sh.ll
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diff --git a/lib/Target/PowerPC/PPCCTRLoops.cpp b/lib/Target/PowerPC/PPCCTRLoops.cpp
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index e419b9b..819635c 100644
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--- a/lib/Target/PowerPC/PPCCTRLoops.cpp
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+++ b/lib/Target/PowerPC/PPCCTRLoops.cpp
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@@ -369,6 +369,14 @@ bool PPCCTRLoops::mightUseCTR(const Triple &TT, BasicBlock *BB) {
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J->getOpcode() == Instruction::URem ||
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J->getOpcode() == Instruction::SRem)) {
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return true;
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+ } else if (TT.isArch32Bit() &&
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+ isLargeIntegerTy(false, J->getType()->getScalarType()) &&
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+ (J->getOpcode() == Instruction::Shl ||
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+ J->getOpcode() == Instruction::AShr ||
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+ J->getOpcode() == Instruction::LShr)) {
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+ // Only on PPC32, for 128-bit integers (specifically not 64-bit
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+ // integers), these might be runtime calls.
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+ return true;
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} else if (isa<IndirectBrInst>(J) || isa<InvokeInst>(J)) {
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// On PowerPC, indirect jumps use the counter register.
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return true;
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diff --git a/test/CodeGen/PowerPC/ctrloop-sh.ll b/test/CodeGen/PowerPC/ctrloop-sh.ll
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new file mode 100644
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index 0000000..d8e6fc7
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--- /dev/null
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+++ b/test/CodeGen/PowerPC/ctrloop-sh.ll
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@@ -0,0 +1,72 @@
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+; RUN: llc < %s | FileCheck %s
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+target datalayout = "E-m:e-p:32:32-i128:64-n32"
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+target triple = "powerpc-ellcc-linux"
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+
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+; Function Attrs: nounwind
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+define void @foo1(i128* %a, i128* readonly %b, i128* readonly %c) #0 {
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+entry:
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+ br label %for.body
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+
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+for.body: ; preds = %for.body, %entry
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+ %i.02 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
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+ %0 = load i128* %b, align 16
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+ %1 = load i128* %c, align 16
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+ %shl = shl i128 %0, %1
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+ store i128 %shl, i128* %a, align 16
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+ %inc = add nsw i32 %i.02, 1
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+ %exitcond = icmp eq i32 %inc, 2048
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+ br i1 %exitcond, label %for.end, label %for.body
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+
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+for.end: ; preds = %for.body
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+ ret void
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+
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+; CHECK-LABEL: @foo1
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+; CHECK-NOT: mtctr
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+}
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+
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+; Function Attrs: nounwind
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+define void @foo2(i128* %a, i128* readonly %b, i128* readonly %c) #0 {
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+entry:
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+ br label %for.body
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+
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+for.body: ; preds = %for.body, %entry
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+ %i.02 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
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+ %0 = load i128* %b, align 16
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+ %1 = load i128* %c, align 16
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+ %shl = ashr i128 %0, %1
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+ store i128 %shl, i128* %a, align 16
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+ %inc = add nsw i32 %i.02, 1
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+ %exitcond = icmp eq i32 %inc, 2048
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+ br i1 %exitcond, label %for.end, label %for.body
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+
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+for.end: ; preds = %for.body
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+ ret void
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+
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+; CHECK-LABEL: @foo2
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+; CHECK-NOT: mtctr
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+}
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+
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+; Function Attrs: nounwind
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+define void @foo3(i128* %a, i128* readonly %b, i128* readonly %c) #0 {
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+entry:
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+ br label %for.body
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+
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+for.body: ; preds = %for.body, %entry
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+ %i.02 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
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+ %0 = load i128* %b, align 16
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+ %1 = load i128* %c, align 16
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+ %shl = lshr i128 %0, %1
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+ store i128 %shl, i128* %a, align 16
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+ %inc = add nsw i32 %i.02, 1
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+ %exitcond = icmp eq i32 %inc, 2048
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+ br i1 %exitcond, label %for.end, label %for.body
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+
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+for.end: ; preds = %for.body
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+ ret void
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+
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+; CHECK-LABEL: @foo3
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+; CHECK-NOT: mtctr
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+}
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+
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+attributes #0 = { nounwind }
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+
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--
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1.9.3
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